Free training Designing with the IP Integrator Tool

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Registration will be closed on  May 18 at 12:00 CEST

Course Description

In collaboration with Doulos & AMD/Xilinx,  Core|Vision organizes this free course Designing with the IP Integrator Tool.

This free course will help you learn about the IP Integrator Tool learn it’s features and gain the expertise needed to develop, implement, and debug different IP block designs. Use the IP integrator to add and configure the Versal ACAP CIPS block and export the generated hardware and configure the AXI NoC to access DDR memory controllers in Versal ACAP devices

The emphasis of this course is on:

  • Creating an IPI block design using the Vivado Design Suite
  • Creating your own custom IP via the IP packaging flow
  • Using the IP integrator to add and configure the Versal® ACAP CIPS block and then to export the generated programmable device image (PDI)
  • Configuring the AXI network on chip (NoC) to access DDR memory controllers in Versal ACAP devices

Workshop Duration

  • Duration 1 day online
  • Time:
    • 09:00 – 15:00 BST
    • 10:00 – 16:00 CEST

Audience

Software and hardware developers, system architects, AI developers and anyone who wants to learn about the IP Integrator tool.

Prerequisites

  • Basic FPGA and Vivado Design Suite knowledge

Workshop Outline

  • 10:00 – 10:10 Introduction
  • 10:10 – 10:25 Vivado IP Flow
    Customize IP, instantiate IP, and verify the hierarchy of your design IP
  • 10:25 – 10:55 Designing with the IP Integrator
    Use the Vivado IP Integrator to create an IPI subsystem, including a Zynq UltraScale+ MPSoC processing system
  • 10:55 – 11:10 Break
  • 11:10 – 11:30 Block Design Containers in the Vivado IP Integrator
    Describe the block design container (BDC) feature and shows how to create a BDC in the IP Integrator
  • 11:30 – 12:05 Creating and Packaging Custom IP
    Create your own IP and package and include it in the Vivado IP Catalog

  • 12:05 – 12:30 Demo:  Creating and Packaging Custom IP
  • 12:30 – 13:15 Lunch Break
  • 13:15 – 13:35 Versal ACAP: Hardware Platform Development Using the Vivado IP Integrator
    Describes the different Versal ACAP design flows and covers the platform creation process using the Vivado IP integrator
  • 13:35 – 13:55 Versal ACAP: NoC Introduction and Concepts
  • 13:55 – 14:25 Demo: Introduction to the Versal NoC and DDRMCs
  • 14:25 – 14:40 Break
  • 14:40 – 15:00 Debug Flow in an IP Integrator Block Design.
    Insert the debug cores into IP integrator block designs
  • 15:00 – 15:25 Revision Control Systems in the Vivado Design ML
    Use version control systems with Vivado design flows
  • 15:25 – 15:45 Managing IP in Remote Locations
    Store IP and related files remote to the current working project directory
  • 15:45 – 15:55 Wrap-Up

 


Datum
20 mei 2022

Locatie
Online
Your home office

Online

Prijs
€ 0,00

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