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TZID:Europe/Amsterdam
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BEGIN:VEVENT
UID:771@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20251023T093000
DTEND;TZID=Europe/Amsterdam:20251024T133000
DTSTAMP:20251014T042109Z
URL:https://www.core-vision.nl/events/free-online-workshop-designing-with-
 the-versal-adaptive-soc-hardware-debug%e2%9c%85/
SUMMARY:Free Online Workshop: Designing with the Versal Adaptive SoC: Hardw
 are Debug✅
DESCRIPTION:\n\n✅ indicates CONFIRMED TO RUN\nWorkshop Description\nIn co
 llaboration with AMD\, Doulos\, Faster Technology and Core-Vision this fre
 e workshop Designing with the Versal Adaptive SoC: Hardware Debug and will
  be sponsored by AMD.\n\n\n\n\n\n\n\n\n\n\n\nThe Versal™ adaptive SoC fr
 om AMD is multi-featured\, offering unprecedented system level performance
  and integration.\n\n\n\n\n\n\n\n\n\n\n\n\nJoin us for a workshop which ex
 plores the tools and techniques available to debug AMD Versal™ devices. 
 We'll investigate debugging the fabric and hard blocks\, as well as APIs w
 hich provide a Python interface for programming and debugging.\n\n\n\n\n\n
 \n\n\n\n\n\n\nThe workshop is designed to maximize individual engagement a
 nd learning.  Each attendee is encouraged to informally ask pertinent que
 stions throughout\, to actively participate in the learning process.\n\n\n
 \nWhat will I learn?\n\n\n\n\nThe workshop will provide you with an unders
 tanding of:\n\n 	The different tool flows for AMD Versal devices\n 	The de
 bug interfaces in the Versal devices\n 	The different debug IP cores\, suc
 h as the AXIS ILA and AXISVIO cores\n 	The different hard block debugging 
 tools\n 	Versal device debugging techniques for JTAG lowspeed debug and hi
 gh-speed debug port (HSDP) debug\n 	ChipScoPy APIs for hardware debugging\
 n\n\n\n\n\n\n\n\nRegister\n\n\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 24/03/versal-webinar.jpg
CATEGORIES:AI,AMD,DSP,FPGA,IP,KRIA,ML,MPSoC,Versal,Vision,Vitis,Vivado,Wor
 kshop
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TZID:Europe/Amsterdam
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DTSTART:20250330T030000
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