Expert VHDL Verification
Expert VHDL Verification is a 3 days course as part of the intensive 5-day Expert VHDL class.
- Expert VHDL Verification (3 days) is for design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification. Advanced VHDL language constructs are presented using a practical testbench methodology as an example. The alternative OSVVM and UVVM methodologies are then introduced and all three methodologies compared and contrasted.
The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.
Who should attend?
- Design engineers wishing to improve the efficiency of their hardware designs and increase productivity
- Design and verification engineers who want to structure and write effective test environments to verify complex designs and systems
What will you learn?
- The principles and details of how to approach the problem of design verification using VHDL
- How to structure and write large and complex VHDL structured verification environments
- The OSVVM and UVVM VHDL verification methodologies
This is an advanced language and methodology training class. Prior attendance of the Doulos Comprehensive VHDL class (or equivalent) is required, and at least 6 months of ‘live’ project experience using VHDL is strongly recommended. Delegates attending the Expert Design Verification module must have knowledge and experience of register transfer level coding and synthesis using VHDL.
03 maart 2021 - 05 maart 2021
Online or Heesch
44 Xilinx Training Credits
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