Expert VHDL Design
Expert VHDL Design is a 2 days class part of the intensive 5-day Expert VHDL class.
- Expert VHDL Design (2 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL, and to improve their VHDL coding style with design maintainability and re-use in mind. Design for Verification is also covered with an introduction to modern assertion-based techniques.
The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time, and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.
Who should attend?
- Design engineers wishing to improve the efficiency of their hardware designs and increase productivity
28 juni 2017 - 29 juni 2017
30 Xilinx Training Credits
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