BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//wp-events-plugin.com//7.2.3.1//EN
TZID:Europe/Amsterdam
X-WR-TIMEZONE:Europe/Amsterdam
BEGIN:VEVENT
UID:1137@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20261109T090000
DTEND;TZID=Europe/Amsterdam:20261113T170000
DTSTAMP:20251210T090503Z
URL:https://www.core-vision.nl/events/expert-vhdl-6/
SUMMARY:Expert VHDL
DESCRIPTION:Course Description\nExpert VHDL is an intensive 5-day advanced 
 application class. It teaches engineers how to increase productivity by en
 hancing their knowledge of the VHDL language itself and its application fo
 r design and verification. Presented in two distinct course modules\, Expe
 rt VHDL focuses on language and synthesis issues\, design maintainability 
 and re-use\, structured verification environments and the latest technique
 s for verification - including an introduction to OVL/PSL and introduction
 s to OSVVM and UVVM.\n\n 	Expert VHDL Design (2 days) is for design engine
 ers wishing to deepen their knowledge of RTL synthesis using VHDL\, and to
  improve their VHDL coding style with design maintainability and re-use in
  mind. This section also includes the introduction to OVL/PSL.\n 	Expert V
 HDL Verification (3 days) is for design engineers and verification enginee
 rs involved in VHDL test bench development or behavioural modelling for th
 e purpose of functional verification. Advanced VHDL language constructs ar
 e presented using a practical testbench methodology as an example. The alt
 ernative OSVVM and UVVM methodologies are then introduced and all three me
 thodologies compared and contrasted.\n\nThe modules\, which may be attende
 d together or independently\, follow on from the industry standard class\,
  Comprehensive VHDL. Carefully designed workshops comprise approximately 5
 0% of teaching time\,.and enable engineers to apply their new skills in th
 e context of the latest VHDL design tools\, practices and methodologies.\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 24/03/scripting.jpg
CATEGORIES:Doulos,VHDL
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net
 herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo:
 0,0
END:VEVENT
BEGIN:VTIMEZONE
TZID:Europe/Amsterdam
X-LIC-LOCATION:Europe/Amsterdam
BEGIN:STANDARD
DTSTART:20261025T020000
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
END:STANDARD
END:VTIMEZONE
END:VCALENDAR