Expert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase productivity by enhancing their knowledge of the VHDL language itself and its application for design and verification. Presented in two distinct course modules, Expert VHDL focuses on language and synthesis issues, design maintainability and re-use, structured verification environments and the latest techniques for verification – including an introduction to OVL/PSL and introductions to OSVVM and UVVM.
- Expert VHDL Design (2 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL, and to improve their VHDL coding style with design maintainability and re-use in mind. This section also includes the introduction to OVL/PSL.
- Expert VHDL Verification (3 days) is for design engineers and verification engineers involved in VHDL test bench development or behavioural modelling for the purpose of functional verification. Advanced VHDL language constructs are presented using a practical testbench methodology as an example. The alternative OSVVM and UVVM methodologies are then introduced and all three methodologies compared and contrasted.
The modules, which may be attended together or independently, follow on from the industry standard class, Comprehensive VHDL. Carefully designed workshops comprise approximately 50% of teaching time,.and enable engineers to apply their new skills in the context of the latest VHDL design tools, practices and methodologies.
- Design engineers wishing to improve the efficiency of their hardware designs and increase productivity
- Design and verification engineers who want to structure and write effective test environments to verify complex designs and systems
What will you learn?
- A set of VHDL language features that go beyond what is taught on a basic training class
- A deeper understanding of how to apply VHDL language for design
- enabling you to troubleshoot VHDL simulation and synthesis problems with ease
- enabling code re-use
- The principles and details of how to approach the problem of design verification using VHDL
- How to structure and write large and complex VHDL structured verification environments
- The OSVVM and UVVM VHDL verification methodologies
This is an advanced language and methodology training class. Prior attendance of the Doulos Comprehensive VHDL class (or equivalent) is required,.and at least 6 months of ‘live’ project experience using VHDL is strongly recommended. Delegates attending the Expert Design module must have knowledge and experience of register transfer level coding and synthesis using VHDL
Doulos training materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world.and has made them sought after resources in their own right. Class fees include:
- Fully indexed class notes creating a complete reference manual
- Workbook full of practical examples to help you apply your knowledge
- Doulos Golden Reference Guide for language, syntax, semantics and tips
- Tour guides (to support the tools and technologies of your choice).
19 juli 2021 - 23 juli 2021
Online or Heesch
63 Xilinx Training Credits
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