Course Description

Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture.

This course covers ISE software features such as the CORE Generator® interface, I/O planning, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.

For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.

Release Date

August 2014

Level

FPGA 2

Training Duration

1 day

Who should attend?

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Recommended RELs

• Architecture Wizard and I/O Planning

Prerequisites

• Working HDL knowledge (VHDL or Verilog)
• Digital design experience

Other Optional RELs

• Basic HDL Coding Techniques
• Virtex-6 and Spartan-6 FPGA HDL Coding Techniques

Software Tools

• Xilinx ISE Design Suite: Logic or System Edition 14.7

Hardware

• Architecture: 7 series FPGAs*
• Demo board (optional): Kintex®-7 FPGA KC705 board*

* This course focuses on the 7 series architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Take advantage of the primary features of the 7 series FPGAs
• Use the PlanAhead™ tool to implement and simulate an FPGA design
• Read reports and determine whether your design goals were met
• Use the Clocking Wizard to create MMCM instantiations
• Use I/O planning to make good pin assignments
• Use the Xilinx Constraints Editor to enter global timing constraints

Course Outline

• Course Agenda
• Basic FPGA Architecture
• Xilinx Tool Flow
• Lab 1: Xilinx Tool Flow
• Reading Reports
• Lab 2: Clocking Wizard and Pin Assignment
• Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool
• Global Timing Constraints
• Lab 4: Global Timing Constraints
• Synchronous Design Techniques
• Course Summary

Lab Descriptions

• Lab 1: Xilinx Tool Overview – Create a new project in the PlanAhead tool and use the ISim simulator to perform behavioral simulation. Implement the design using default software options and download to the evaluation board.
• Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize an MMCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design.
• Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Use the Design Rule Checker to follow the I/O banking rules.
• Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.