Essential Digital Design Techniques
Essential Digital Design Techniques is a fast-track,.application orientated course designed to bridge the gap between text book theory and real world digital design practice.
It significantly accelerates the on-the-job learning curve for engineers new to digital design,.or those needing to refine their design skills before project involvement. With a strong emphasis on practical design and hands-on workshops,.this course has been specifically developed to capture design techniques usually learned over months, in an intensive 2-day format.
Essential Digital Design Techniques provides the ideal first stage in full scale project training for graduate design engineers,.or engineers moving into digital design from other disciplines (including software or analog design). As such, it is the natural precursor to the Doulos Comprehensive VHDL and Comprehensive Verilog courses,.which prepare engineers for HDL application within FPGA or ASIC design projects.
- New graduate engineers embarking on a first project, or engineers with limited practical experience of digital design.
- Engineers from other disciplines (e.g. software design or analog design)
- Engineers re-training for digital design involvement, or requiring familiarization with modern digital design techniques
Delegates require no prior involvement in digital design projects or HDL knowledge. They should be familiar with the basic principles of digital electronics. Some background refresher reading can be suggested prior to the course if required (contact Core|Vision for details).
What you will learn
- Combinational and Sequential Logic Design for PLDs and ASICs, with an emphasis on synchronous design techniques
- How to design and implement fundamental structures e.g. decoders, multiplexers, shift registers, counters
- How to design and implement synchronous Finite State Machines
- An overview of ASIC and field programmable logic design including a survey of state of the art devices
- Designing with programmable devices
- Effective Design methodologies and flows
PLEASE NOTE: this course does not teach, or require knowledge in a specific Hardware Description Language.
25 mei 2021 - 26 mei 2021
Online or Heesch
30 Xilinx Training Credits
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