Developing AI Inference Solutions with the Vitis AI Platform

Course Description

This course describes how to use the Vitis™ AI development platform in conjunction with DNN algorithms, models, inference and training, and frameworks on cloud and edge computing platforms.

The emphasis of this course is on:

  • Illustrating the Vitis AI tool flow
  • Utilizing the architectural features of the Deep Learning Processor Unit (DPU)
  • Optimizing a model using the AI quantizer and AI compiler
  • Utilizing the Vitis AI Library to optimize pre-processing and post-processing functions
  • Creating a custom platform and application
  • Deploying a design

What’s New for 3.5

  • Focus on TensorFlow 2, PyTorch, and some ONNX
  • All labs have been updated to the latest software versions

 

Level

AI 3

Course Duration

2 day

Audience

Software and hardware developers, AI/ML engineers, data scientists, and anyone who needs to accelerate their software applications using Xilinx devices

Prerequisites

Software Tools

  • Vitis AI development environment 3.5
  • Vivado Design Suite 2023.1

Hardware

  • Alveo accelerator cards and adaptive SoCs
  • Zynq UltraScale+ MPSoC ZCU104 board*

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe machine learning solutions from the perspective of the Vitis AI development tools
  • Enumerate the supported frameworks and models for cloud and edge applications
  • Implement neural networks on cloud and edge platforms using the Vitis AI development platform
  • Describe the proper Vitis AI tool flow
  • Optimize a DPU for edge applications, leveraging the device architecture
  • Enumerate the APIs included with the AMD Xilinx AI Library
  • Create a custom hardware overlay based on application requirements
  • Create a custom application using a custom hardware overlay and deploy the design

Course Outline

Day 1

  • Introduction to the Vitis AI Development Environment –  Describes the Vitis AI development environment, which consists of the Vitis AI development kit, for AI inference on AMD Xilinx hardware platforms, including both edge devices and Alveo accelerator cards. {Lecture}
  • Frameworks Supported by the Vitis AI Development Environment – Discusses the support for many common machine learning frameworks such as Caffe, TensorFlow, and Pytorch. {Lecture}
  • Setting Up the Vitis AI Development Environment – Demonstrates the steps to set up a host machine for developing and running AI inference applications on cloud or embedded devices. {Demo}
  • Overview of ML Concepts – Overview of ML concepts such as DNN algorithms, models, inference and training, and frameworks. {Lecture}
  • AI Optimize – Describes the optimization of a trained model that can prune a model up to 90%. This topic is for advanced users and will be covered in detail in the Advanced ML training course. {Lecture}
  • AI Quantizer and AI Compiler – Describes the AI quantizer, which supports model quantization, calibration, and fine tuning. Also describes the AI compiler tool flow. With these tools, deep learning algorithms can deploy in the Deep Learning Processor Unit (DPU), which is an efficient hardware platform running on an AMD Xilinx FPGA or SoC. {Lecture, Lab}
  • AI Profiler – Describes the AI profiler, which provides layer-by-layer analysis to help with bottlenecks. Also covers debugging the DPU running result. {Lecture}
  • Introduction to the Deep Learning Processor Unit (DPU) – Describes the Deep Learning Processor Unit (DPU) and its variants for edge and cloud applications. {Lecture}
  • DPUCZDX8G Architecture Overview – Overview of the DPUCZDX8G architecture, supported CNN operations, DPU data flow, and design considerations. {Lecture}

Day 2

  • Vitis AI Library – Reviews the Vitis AI Library, which is a set of high-level libraries and APIs built for efficient AI inference with the DPU. It provides an easy-to-use and unified interface for encapsulating many efficient and high-quality neural networks. {Lecture, Labs} Note that the edge flow version of the lab is not available in the OnDemand curriculum because an evaluation board is required for the entirety of the lab.
  • Creating a Custom Hardware Platform with the DPU Using the Vivado Design Suite Flow (Edge) – Illustrates the steps to build a Vivado Design Suite project, add the DPUCZDX8G IP, and run the design on a target board. {Lab}
  • Creating a DPU Kernel Using the Vitis Environment Flow (Edge) – Illustrates the steps to build a Vitis unified software platform project that adds the DPU as the kernel (hardware accelerator) and to run the design on a target board. {Lab}
  • Creating a Vitis Embedded Acceleration Platform (Edge) – Describes the Vitis embedded acceleration platform, which provides product developers an environment for creating embedded software and accelerated applications on heterogeneous platforms based on FPGAs, Zynq® SoCs, and Alveo data center cards. {Lecture}
  • Creating a Custom Application (Edge) – Illustrates the steps to create a custom application, including building the hardware and Linux image, optimizing the trained model, and using the optimized model to accelerate a design. {Lab}

AI


Date
27 February 2024 - 28 February 2024

Location
Core|Vision
Cereslaan 24
5384 VT
Heesch

Price
€ 0,00
or
20 Xilinx Training Credits

Information
Training brochure

Registration form

Registration on demand, please contact us.