Designing with Xilinx Serial Transceivers ONLINE
Standard Level – 4 sessions CEST time: 10:00 – 14:00
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content as a scheduled face-to face class and delivers comparable learning outcomes. Daily sessions comprise 4-6 hours of class contact time.
In this four-session course, you will learn how to employ serial transceivers in your 7 series, UltraScale™, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC design. You will identify and use the features of the serial transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection.
Additional topics include use of the Transceivers Wizards, synthesis and implementation considerations, board design as it relates to the transceivers, and testing and debugging. This course combines lectures with practical hands-on labs.
Who Should Attend?
- Verilog or VHDL experience (or Comprehensive Verilog or Comprehensive VHDL course)
- Familiarity with logic design (state machines and synchronous design)
- Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
- VivadoÂ® System Edition 2016.3
- Mentor Graphics Questa Advanced Simulator 10.4
- Architecture: 7 series and UltraScale FPGAs*
- Demo board: Kintex® UltraScale FPGA KCU105 board or Kintex-7 FPGA KC705 board*
- Describe and utilize the ports and attributes of the serial transceiver in Xilinx FPGAs and MPSoCs
- Effectively utilize the following features of the gigabit transceivers:
- 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
- Pre-emphasis and receive equalization
- Use the Transceivers Wizards to instantiate GT primitives in a design
- Access appropriate reference material for board design issues involving signal integrity and the power supply, reference clocking, and trace design
- Use the IBERT design to verify transceiver links on real hardware
- Course Agenda
- 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Overview
- 7 Series, UltraScale, UltraScale+, Zynq UltraScale+ Transceivers Clocking and Resets
- Transceiver IP Generation â€“ Transceiver Wizard
- Transceiver Simulation
- PCS Layer General Functionality
- PCS Layer Encoding
- Lab 1: Transceiver Core GenerationUse the Transceivers Wizard to create instantiation templates
- Lab 2: Transceiver SimulationSimulate the transceiver IP by using the IP example design
- Lab 3: 64B/66B EncodingGenerate a 64B/66B transceiver core by using the Transceivers Wizard, simulate the design, and analyze the results
- Transceiver Implementation
- PMA Layer Details
- PMA Layer Optimization
- Lab 4 (demo only): IBERT DesignVerify transceiver links on real hardware
- Lab 5: Transceiver ImplementationImplement the transceiver IP by using the IP example design
- Transceiver Test and Debugging
- Transceiver Board Design Considerations
- Transceiver Application Examples
- Course summary
- Lab 6 (part demo): Transceiver DebuggingDebug transceiver links
- Lab 1:Transceiver Core Generation –Use the Transceivers Wizard to create instantiation templates.
- Lab 2: Transceiver Simulation –Simulate the transceiver IP by using the IP example design.
- Lab 3: 64B/66B Encoding –Generate a 64B/66Btransceiver core by using the Transceivers Wizard, simulate the design, and analyze the results.
- Lab 4: Transceiver Implementation –Implement the transceiver IP by using the IP example design.
- Lab 5: IBERT Design –Verify transceiver links on real hardware.
- Lab 6: Transceiver Debugging –Debug transceiver links.
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07 juli 2020 - 10 juli 2020
Your home office
28 Xilinx Training Credits
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