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UID:1103@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20260430T090000
DTEND;TZID=Europe/Amsterdam:20260501T170000
DTSTAMP:20251210T084630Z
URL:https://www.core-vision.nl/events/designing-with-xilinx-serial-transce
 ivers-4/
SUMMARY:Designing with Xilinx Serial Transceivers
DESCRIPTION:Course Description\nLearn how to employ serial transceivers in 
 UltraScale™\, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC designs.\n
 The focus is on:\n\n 	Identifying and using the features of the serial tra
 nsceiver blocks\, such as 8B/10B and 64B/66B encoding\, channel bonding\, 
 clock correction\, and comma detection.\n 	Utilizing the Transceivers Wiza
 rds to instantiate transceiver primitives.\n 	Synthesizing and implementin
 g transceiver designs.\n 	Taking into account board design as it relates t
 o the transceivers.\n 	Testing and debugging.\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 24/04/high-speed-serial-banner-e1718949231123.png
CATEGORIES:AI,AMD,Connectivity,DSP,Embedded,FPGA,KRIA,MPSoC,Vivado,Zynq
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
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 herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo:
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DTSTART:20260329T030000
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