Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2)

Course Description

This course describes the system design flow and interfaces that can be used for data movement in the Versal™ AI Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster development.
In addition, advanced features in adaptive data flow (ADF) graph implementation, such as using streams, cascade streams, buffer location constraints, runtime parameterization, and APIs to update and read runtime parameters, are covered. The course also highlights how to utilize the Vitis™ Model Composer tool for AI Engine designs.

The emphasis of this course is on:

  • Implementing a system-level design flow (PS + PL + AIE) and the supported simulation
  • Using an interface for data movement between the PL and AI Engine
  • Utilizing AI Engine APIs for arithmetic operations and advanced MAC intrinsics to implement filters
  • Utilizing the AI Engine DSP library for faster development
  • Applying advanced features for optimizing a system-level design
  • Utilizing the Vitis Model Composer tool for AI Engine designs

What’s New for 2023.1

  • System Design Flow module: Added information on the Vitis export to Vivado™ flow and the methodology for resetting and reloading AI Engine arrays
  • New labs:
    ▪ Vitis Export to Vivado Flow
    ▪ Designing Filters Using the AI Engine DSP Library in Vitis Model Composer
    ▪ All labs have been updated to the latest software versions

Level

ACAP 3

Course Duration

2 day

Audience

Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using Xilinx devices

Prerequisites

  • Comfort with the C/C++ programming language
  • Software development flow
  • Vitis software for application acceleration development flow

Software Tools

  • Vitis unified software platform 2023.1

Hardware

  • Architecture: Versal adaptive SoCs

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
  • Describe the supported emulation for a system-level design
  • Describe the data movement between the PS, PL, and AI Engines
  • Describe the implementation of the AI Engine and programmable logic
  • Implement a system-level design for Versal ACAPs with the Vitis tool flow
  • Utilize advanced MAC intrinsic syntax and application-specific intrinsics such as DDS and FFT
  • Utilize the AI Engine DSP library for faster development
  • Apply location constraints on kernels and buffers in the AI Engine array
  • Apply runtime parameters to modify application behavior
  • Debug a system-level design
  • Utilize the AI Engine library in Vitis Model Composer for AI Engine development

Course Outline

Day 1

  • Versal Adaptive SoC: Application Partitioning 1 (Review) – Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP. {Lecture}
  • Versal Adaptive SoC: Application Partitioning 2 – Explains how image and video processing can be targeted for the Versal ACAP by utilizing the different engines (Scalar Engine, Adaptable Engine, and Intelligent Engine). Also describes the AI engine development flow. {Lecture}
  • Versal Adaptive SoC: Data Communications 1 – Describes the implementation of AI Engine and programmable logic (PL) kernels and how to implement the functions in the AI Engine that take advantage of low power. {Lecture}
  • Versal Adaptive SoC: Data Communications 2 – Describes the programming model for the implementation of stream interfaces for the AI Engine kernels and PL kernels. Lists the stream data types that are supported by AI Engine and PL kernels. {Lecture}
  • System Design Flow – Demonstrates the Vitis compiler flow to integrate a compiled AI Engine design graph (libadf.a) with additional kernels implemented in the PL region of the device (including HLS and RTL kernels) and link them for use on a target platform. You can call then these compiled hardware functions from a host program running in the Arm® processor in the Versal device or on an external x86 processor. {Lecture, Lab}
  • Introduction to AI Engine APIs for Arithmetic Operations – Describes the Versal AI Engine APIs for arithmetic, comparison, and reduction operations. For advanced users, describes how to implement filters using advanced intrinsics functions for various filters, such as nonsymmetric FIRs, symmetric FIRs, or halfband decimators. {Lecture}

Day 2

  • AI Engine: DSP Library Overview – Provides an overview of the available DSP library, which enables faster development and comes with ready-to-use example designs that help with using the library and tools. {Lecture, Labs}
  • Advanced Graph Input Specifications 1 – Learn advanced features such as using initialization functions, writing directly using streams from the AI Engine, cascade stream, core location constraints, and buffer location constraints. {Lecture}
  • Advanced Graph Input Specifications 2 – Describes how to implement runtime parameterization, which can be used as adaptive feedback and to switch functionality dynamically. {Lecture, Lab}
  • Versal AI Engine Application Debug and Trace – Shows to how to debug the AI Engine application running on the Linux OS and how to debug via hardware emulation that allows simulation of the application. {Lecture}
  • Vitis Model Composer for AI Engine DevelopmentDescribes Vitis Model Composer is and how to use the available libraries for AI Engine design development. {Lecture}

ACAP


Date
13 March 2024 - 14 March 2024

Location
Core|Vision
Cereslaan 24
5384 VT
Heesch

Price
€ 2.000,00
or
20 Xilinx Training Credits

Information
Training brochure

Registration form

Tickets

AIE-GRAPH

€ 2.000,00

Registratiegegevens

Booking Summary

1
x Standaardticket
€ 2.000,00
Total Price
€ 2.000,00