Designing with UltraScale FPGA Transceivers
FPGA designers and logic designers
- Verilog or VHDL experience or the Designing with Verilog or Designing with VHDL course
- Familiarity with logic design (state machines and synchronous design)
- Basic knowledge of FPGA architecture and Xilinx implementation tools is helpful
- Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful
- Vivado® System Edition 2015.3
- Mentor Graphics QuestaSim simulator 10.4
- Architecture: UltraScale FPGAs
- Demo board: None
After completing this comprehensive training, you will know how to:
- Describe and utilize the ports and attributes of the serial transceiver in 7 series FPGAs
- Effectively utilize the following features of the gigabit transceivers:
- 64B/66B and other encoding/decoding, comma detection, clock correction, and channel bonding
- Pre-emphasis and linear equalization
- Use the UltraScale FPGAs Transceivers Wizard to instantiate GT primitives in a design
- Access appropriate reference material for board design issues involving the power supply, reference clocking, and trace design
- Use the IBERT design to verify transceiver links on real hardware
- UltraScale FPGAs Overview
- UltraScale FPGAs Transceivers Overview
- UltraScale FPGAs Transceivers Clocking and Resets
- Transceiver Wizard Overview
- Lab 1: Transceiver Core Generation
- Transceiver Simulation
- Lab 2: Transceiver Simulation
- PCS Layer General Functionality
- PCS Layer Encoding
- Lab 3: 64B/66B Encoding
- Transceiver Implementation
- Lab 4: Transceiver Implementation
- PMA Layer Details
- Transceiver Board Design Considerations
- Transceiver Test and Debugging
- Lab 5: IBERT Design
- Transceiver Application Examples
- Lab 1: Transceiver Core Generation – Use the UltraScale FPGAs Transceivers Wizard to create instantiation templates.
- Lab 2: Transceiver Simulation – Simulate the transceiver IP by using the IP example design.
- Lab 3: 64B/66B Encoding –.Generate a 64B/66B transceiver core by using the UltraScale FPGAs Transceivers Wizard, simulate the design, and analyze the results.
- Lab 4: Transceiver Implementation – Implement the transceiver IP by using the IP example design.
- Lab 5: IBERT Design – Verify transceiver links on real hardware.
20 juni 2019 - 21 juni 2019
18 Xilinx Training Credits
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