Designing with the Versal Adaptive SoC: Serial Transceivers

Designing with the Versal Adaptive SoC: Serial Transceivers

When

On request     

Reserve

€1.000,00
 / 10  Training Credits
On request

Where

Core-Vision
Cereslaan 24, 5384 VT, Heesch
Nederland

Event type

Information

Kaart niet beschikbaar

Course Description

This course provides a system-level understanding of AMD Versal™ adaptive SoC serial transceivers. Transceiver architecture, IP generation, simulation, and implementation are covered. Additional information on PCB design issues is also covered.
The focus is on:

  • Constructing a system using Versal device serial transceivers by:
    ▪ Selecting the appropriate IP for an application
    ▪ Configuring Transceivers Wizard IPs
    ▪ Using transceiver IP example designs
    ▪ Simulating and implementing transceiver IPs
  • Identifying the advanced capabilities of the serial transceivers, including using IBERT and eye scan options
  • Accessing the appropriate reference material for board design issues involving signal integrity, the power supply, reference clocking, and trace design


Level

ACAP 3

Training Duration

1 day

Audience

  • Hardware designers who want to create applications using serial transceivers
  • System architects who want to leverage the key advantages of serial transceivers

Prerequisites

  • Knowledge of Verilog or VHDL
  • Familiarity with logic design (state machines and synchronous design)
  • Some experience with Vivado™ implementation
  • Some experience with a simulation tool, preferably the Vivado simulator
  • Familiarity with serial I/O basics and high-speed serial I/O standards is also helpful

Software Tools

  • Vivado Design Suite 2023.1

Hardware

  • Architecture: All Versal adaptive SoC devices
  • Evaluation board: Versal VCK190 board

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe and utilize the building blocks of the serial transceivers in the Versal devices
  • Describe and utilize the ports and attributes of the transceivers
  • Design, simulate, and implement the transceivers
  • Utilize transceiver debugging options
  • Identify transceiver use cases
  • Describe transceiver board design requirements

Course Outline

Day 1

  • Course Introduction - Introduces the course and discusses serial transmission. {Lecture}
  • Serial Transceiver Shared Features - Describes the structure and shared features, such as clocking and reset schemes, of the Versal device serial transceivers. {Lecture}
  • Serial Transceiver Architecture - Discusses the architecture and functionality of the transmit and receive functional blocks. {Lecture}
  • Transceiver IP Generation - Demonstrates usage of the Transceivers Wizard. {Lecture, Lab}
  • Transceiver IP Simulation - Covers how to perform transceiver design simulation. {Lecture, Lab}
  • Transceiver IP Implementation - Illustrates how to perform transceiver implementation. {Lecture,Lab}
  • Transceiver Use Cases - Discusses using the transceivers for several protocol applications, including the PCI Express®, Ethernet, Interlaken, JESD204, and Aurora interfaces. {Lecture}
  • Transceiver Board Design - Describes board design issues involving signal integrity, the power supply, reference clocking, and trace design. {Lecture}
  • GTM Transceiver - Reviews GTM transceiver-specific design generation and simulation. {Lecture, Lab}

Request

Tickets

€1.000,00

Registration information


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