BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//wp-events-plugin.com//7.2.3.1//EN
TZID:Europe/Amsterdam
X-WR-TIMEZONE:Europe/Amsterdam
BEGIN:VEVENT
UID:1041@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20260109T090000
DTEND;TZID=Europe/Amsterdam:20260109T170000
DTSTAMP:20251210T075855Z
URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s
 oc-serial-transceivers-3/
SUMMARY:Designing with the Versal Adaptive SoC: Serial Transceivers
DESCRIPTION:Course Description\nThis course provides a system-level underst
 anding of AMD Versal™ adaptive SoC serial transceivers. Transceiver arch
 itecture\, IP generation\, simulation\, and implementation are covered. Ad
 ditional information on PCB design issues is also covered.\nThe focus is o
 n:\n\n 	Constructing a system using Versal device serial transceivers by:\
 n▪ Selecting the appropriate IP for an application\n▪ Configuring Tran
 sceivers Wizard IPs\n▪ Using transceiver IP example designs\n▪ Simulat
 ing and implementing transceiver IPs\n 	Identifying the advanced capabilit
 ies of the serial transceivers\, including using IBERT and eye scan option
 s\n 	Accessing the appropriate reference material for board design issues 
 involving signal integrity\, the power supply\, reference clocking\, and t
 race design\n\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 24/04/high-speed-serial-banner-e1718949231123.png
CATEGORIES:Connectivity,FPGA,Versal,Vivado
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net
 herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo:
 0,0
END:VEVENT
BEGIN:VTIMEZONE
TZID:Europe/Amsterdam
X-LIC-LOCATION:Europe/Amsterdam
BEGIN:STANDARD
DTSTART:20251026T020000
TZOFFSETFROM:+0200
TZOFFSETTO:+0100
TZNAME:CET
END:STANDARD
END:VTIMEZONE
END:VCALENDAR