Designing with the Versal Adaptive SoC: Quick Start
Course Description
Explore the AMD Versal™ adaptive SoC heterogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Versal devices. Gain knowledge of embedded software development and application partitioning. Also learn how to perform system migration to the Versal architecture.
The emphasis of this course is on:
- Reviewing the architecture of the Versal adaptive SoC
- Describing the different compute resources available in the Versal architecture
- Demonstrating the embedded software development flow for Versal devices
- Describing the architectures of the network on chip (NoC) and AI Engine
- Explaining application partitioning based on the models of computation
- Comparing various functional blocks of the Versal devices to previous-generation devices
What's New for 2024.1
- Versal Adaptive SoC - Application Mapping and Partitioning module: Updated with the system design planning flow
- All the labs have been updated to the latest software versions
Level
ACAP 1
Course Duration
1 day
Audience
Software and hardware developers, system architects, and anyone who wants to learn about the architecture and programming of the Versal adaptive SoC
Prerequisites
- Basic knowledge of AMD FPGAs and adaptive SoCs
- Basic knowledge of the Vivado™ and Vitis toolsComfort with the C/C++ programming language
Software Tools
- Vitis Unified IDE 2024.1
- Vivado Design Suite 2024.1
Hardware
- Architecture: Versal adaptive SoCs
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
- Describe the AMD Versal architecture
- Describe the Versal design flows
- Describe the embedded software development flow for Versal devices
- Design using the network on chip (NoC)
- Create a simple AI Engine application
- Follow the high-level system migration recommendations provided in this course
Course Outline
Day 1
- Introduction - Describes the need for Versal devices and offers an overview of the Versal portfolio. {Lecture}
- Architecture Overview - Provides a high-level overview of the Versal architecture, illustrating the various compute resources available in the Versal architecture. {Lecture}
- Design Tool Flow - Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}
- Embedded Software Development - Describes the software development environments and embedded software development flows for Versal devices. Also introduces embedded software debugging. {Lecture}
- NoC Introduction and Concepts - Covers the reasons to use the network on chip, its basic elements, and common terminology. {Lecture, Lab}
- AI Engine - Discusses the AI Engine array architecture, terminology, and AI Engine interfaces. {Lecture, Lab}
- Application Mapping and Partitioning - Covers the system design methodology and describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal adaptive SoC. Also describes what application partitioning is and how an application can be accelerated by using the various compute domains in the Versal device. {Lecture}
- System Migration - Compares the various functional blocks of the Versal devices to previous-generation devices. Describes the migration of designs from the UltraScale™ and UltraScale+™ architectures to the Versal architecture. {Lecture