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TZID:Europe/Amsterdam
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UID:1140@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20261202T090000
DTEND;TZID=Europe/Amsterdam:20261202T170000
DTSTAMP:20251210T090559Z
URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s
 oc-network-on-chip-6/
SUMMARY:Designing with the Versal Adaptive SoC: Network on Chip
DESCRIPTION:Course Description\nThis course introduces the AMD Versal™ ne
 twork on chip (NoC) to users familiar with other SoC architectures. Beside
 s providing an overview of the major components in the Versal device\, the
  course illustrates how the NoC can be configured to access DDR memory con
 trollers and HBM memory controllers.\n\nThe emphasis of this course is on:
 \n\n 	Enumerating the major components comprising the NoC architecture in 
 the Versal ACAP\n 	Implementing a basic Versal NoC design using the Vivado
 ™ IP integrator\n 	Accessing the Versal NoC using the modular NoC flow\n
  	Configuring the DDR memory controller for accessing DDR memory\n 	Config
 uring and tunning the NoC for efficient data movement\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 24/08/versal-workshop-2024-take-2.jpg
CATEGORIES:AI,AMD,Connectivity,DSP,Embedded,ML,System,Versal,Vitis,Vivado
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net
 herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo:
 0,0
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TZID:Europe/Amsterdam
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DTSTART:20261025T020000
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