BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//wp-events-plugin.com//7.2.3.1//EN
TZID:Europe/Amsterdam
X-WR-TIMEZONE:Europe/Amsterdam
BEGIN:VEVENT
UID:1107@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20260528T090000
DTEND;TZID=Europe/Amsterdam:20260529T170000
DTSTAMP:20251210T085100Z
URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s
 oc-memory-interfaces-4/
SUMMARY:Designing with the Versal Adaptive SoC: Memory Interfaces
DESCRIPTION:Course Description\nThis course provides a system-level underst
 anding of AMD Versal™ adaptive SoC memory interfaces. Memory controller 
 architecture\, IP generation\, simulation\, and implementation are covered
 . Additional information on PCB design issues is also covered\nThe emphasi
 s is on:\n\n 	Constructing a system using Versal adaptive SoC external mem
 ory interfaces by:\n\n 	Selecting the appropriate IP for an application\n 
 	Configuring the memory controller IPs\n 	Using the memory controllers in 
 test benches and applications\n 	Simulating and implementing the memory co
 ntroller IPs\n\n\n 	Exploring traffic pattern generation\n 	Performance tu
 ning for the hardened DDRMC\n 	Accessing the appropriate reference materia
 l for board design issues involving signal integrity\, the power supply\, 
 reference clocking\, and trace design\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 24/04/Versal_Product-Shot.jpg
CATEGORIES:AMD,Board,Connectivity,Embedded,FPGA,Hardware,Versal,Vitis,Viva
 do
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net
 herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo:
 0,0
END:VEVENT
BEGIN:VTIMEZONE
TZID:Europe/Amsterdam
X-LIC-LOCATION:Europe/Amsterdam
BEGIN:DAYLIGHT
DTSTART:20260329T030000
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
END:DAYLIGHT
END:VTIMEZONE
END:VCALENDAR