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TZID:Europe/Amsterdam
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UID:1213@core-vision.nl
DTSTART;TZID=Europe/Amsterdam:20260722T090000
DTEND;TZID=Europe/Amsterdam:20260722T170000
DTSTAMP:20260331T093750Z
URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s
 oc-hardware-debug-3/
SUMMARY:Designing with the Versal Adaptive SoC: Hardware Debug
DESCRIPTION:Course Description\nThis course describes the tools and techniq
 ues available to debug AMD Versal™ devices. You will learn about feature
 s for debugging the fabric (programmable logic) and the hard blocks. The c
 ourse also covers ChipScoPy APIs\, which provide a Python™ interface to 
 program and debug the Versal devices.\nThe emphasis is on:\n\n 	Describing
  the Versal device design flows\n 	Enumerating the Versal device debug fea
 tures for programmable logic (PL) and hard block debugging\n 	Debugging th
 e Versal device using different debug IP cores\n 	Using ChipScoPy APIs for
  hardware debugging\n 	Improving Versal device system performance\n\n\n
ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20
 24/08/versal-workshop-2024-take-2.jpg
LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede
 rland
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 herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo:
 0,0
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TZID:Europe/Amsterdam
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DTSTART:20260329T030000
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