Designing with the Versal Adaptive SoC: Architecture

Course Description

Learn about the AMD Versal™ adaptive SoC architecture building blocks, such as Adaptable Engines, high-speed I/O, clocking, Scalar Engines, Intelligent Engines, and the programmable network on chip (NoC). Also learn how to use leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application.

The emphasis of this course is on:

  • Reviewing the architecture of the Versal adaptive SoC
  • Describing the different engines available in the Versal architecture and what resources they contain
  • Describing the architectures of the network on chip (NoC) and AI Engine
  • Outlining the memory solutions and programming interfaces available in the Versal adaptive SoC
  • Identifying the PCI Express® and serial transceiver solutions available in the Versal adaptive SoC

Level

ACAP 1

Course Duration

2 day

Audience

Software and hardware developers, system architects, DSP users, and anyone who wants to learn about the architecture of the Versal adaptive SoC

Prerequisites

  • Basic knowledge of AMD FPGAs and adaptive SoCs
  • Basic knowledge of the Vivado™ and Vitis™ tools

Software Tools

  • Vivado Design Suite 2023.2
  • Vitis unified software platform 2023.2

Hardware

  • Architecture: Versal adaptive SoC
  • Demo board: Versal VCK190 Evaluation Platform

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Describe the Versal adaptive SoC architecture
  • Identify the different engines available in the Versal devices and what resources they contain
  • Utilize the hardened blocks available in the Versal architecture
  • Describe the NoC and AI Engine architectures
  • Outline the memory solutions and programming interfaces available in the Versal adaptive SoC
  • Identify the PCI Express and serial transceiver solutions available in the Versal adaptive SoC
  • Follow the high-level system migration recommendations provided in this course

Course Outline

Day 1

  • Introduction Describes the need for Versal devices and offers an overview of the Versal portfolio. {Lecture}
  • Architecture Overview Provides a high-level overview of the Versal architecture, illustrating the various engines available in the Versal architecture. {Lecture}
  • Design Tool Flow Maps the various engines in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture, Lab}
  • Adaptable Engines (PL) Describes the logic resources available in the Adaptable Engine. {Lecture}
  • SelectIO Resources Describes the I/O bank, SelectIO™ interface, and I/O delay features. {Lecture}
  • Clocking Architecture Discusses the clocking architecture, clock buffers, clock routing, clock management functions, and clock de-skew. {Lecture, Lab}
  • Processing System Reviews the Arm® Cortex®-A72 processor APU and Cortex-R5 processor RPU that form the Scalar Engine. The platform management controller (PMC), processing system manager (PSM), I/O peripherals, and PS-PL interfaces are also covered. {Lecture}
  • PMC and Boot and Configuration Describes the platform management controller, platform loader and manager (PLM) software and boot and configuration. {Lecture, Lab}
  • System Interrupts Discusses the different system interrupts and interrupt controllers. {Lecture}

Day 2

  • Timers, Counters, and RTC Provides an overview of timers and counters, including the system counter, triple timer counter (TTC), watchdog timer, and real-time clock (RTC). {Lecture}
  • DSP Engine Describes the DSP58 slice and compares the DSP58 slice with the DSP48 slice. DSP58 modes are also covered in detail. {Lecture, Lab}
  • AI Engine Discusses the AI Engine array architecture, terminology, and AIE interfaces. {Lecture, Lab}
  • NoC Introduction and Concepts Covers the reasons to use the network on chip, its basic elements, and common terminology. {Lecture, Lab}
  • Memory Solutions Describes the available memory resources, such as block RAM, UltraRAM, LUTRAM, embedded memory, OCM, and DDR. The integrated memory controllers are also covered. {Lecture}
  • Programming Interfaces Reviews the various programming interfaces in the Versal device. {Lecture}
  • PCI Express & CCIX Provides an overview of the CCIX PCIe module and describes the PL and CPM PCIe blocks. {Lecture, Lab}
  • Serial Transceivers Describes the transceivers in the Versal device. {Lecture}
  • System Migration Compares the various functional blocks of the Versal devices to previous-generation devices. Describes the migration of designs from the UltraScale™ and UltraScale+™ architectures to the Versal architecture. {Lecture}

ACAP


Date
25 March 2024 - 26 March 2024

Location
Core|Vision
Cereslaan 24
5384 VT
Heesch

Price
€ 2.000,00
or
20 Xilinx Training Credits

Information
Training brochure

Registration form

Tickets

ACAP-VARCH

€ 2.000,00

Registratiegegevens

Booking Summary

1
x Standaardticket
€ 2.000,00
Total Price
€ 2.000,00