Designing with the Spartan UltraScale+ FPGA: Architecture

Level

FPGA 3

Course Duration

2 days.

Audience

Anyone who would like to build a design for the Spartan UltraScale+ device

Prerequisites

• Designing FPGAs Using the Vivado™ Design Suite 1 course
• Designing with the UltraScale™ and UltraScale+ Architectures course
• Familiarity with the Vivado Design Suite
• Intermediate VHDL or Verilog knowledge

Software Tools

• Vivado Design Suite 2025.1*
• Power Design Manager tool 2025.1

Hardware

• Architecture:Spartan UltraScale+ FPGAs

* Some tool features will be supported future releases.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Describe the key features and fundamental blocks of the AMD Spartan UltraScale+ FPGA architecture
• Describe Spartan UltraScale+ clocking, including buffer types, clock management tiles, and routing for enhanced timing
• Describe the various on-chip memory resources available in the Spartan UltraScale+ architecture
• Utilize the advanced I/O capabilities for various connectivity needs
• Identify the high-speed transceivers for use in applications such as PCIe Gen4
• Explain the configuration process for Spartan UltraScale+ devices
• Outline the platform security framework and advanced security features
• Leverage the Power Design Manager (PDM) tool for power estimation

Course Outline

Day 1

• Introduction to the AMD UltraScale+ Families - Describes how UltraScale+ architectural benefits and features deliver enhanced performance, efficiency, and flexibility across diverse product families. {Lecture}
• Introduction to the AMD Spartan UltraScale+ Architecture - Discusses the key features and fundamental blocks of the Spartan UltraScale+ architecture. {Lecture}
• Programmable Logic - Explores the Spartan UltraScale+ programmable logic architecture, including its core components, enhancements, and advanced routing capabilities. {Lecture}
• Clock Structure and Layout - Illustrates the clocking architecture and available resources in the Spartan UltraScale+ architecture and differentiates the clocking architectures of 7 series, UltraScale, and Spartan UltraScale+ FPGAs. {Lecture, Lab}
• Clock Buffers - Describes the different types of clock buffers. {Lecture}
• Clock Management - Reviews the clock management tiles for clock generation and I/O management. {Lecture}
• Clock Routing - Discusses the clock routing architecture to reduce clock skew and enhance timing. {Lecture}
• Block RAM Memory Resources - Covers the Spartan UltraScale+ architecture block RAM configurations, features, and cascading modes. {Lecture}
• FIFO Memory Resources - Outlines the capabilities of the built-in FIFO. {Lecture}
• UltraRAM Resources - Explains the UltraRAM features and architecture. {Lecture}

Day 2

• I/O Resources: Overview -
  Identifies some of the challenges of using high-speed I/O. Outlines the types and functions of I/O banks available in the Spartan UltraScale+ architecture. {Lecture}
• I/O Resources: Component Mode -Describes component mode and each of its blocks in the IOB. {Lecture, Lab}
• I/O Resources: Native Mode - Describes native mode and its clocking. {Lecture}
• DSP Resources - Explores the architecture and functionality of the DSP48E2 slice in Spartan UltraScale+ FPGAs. {Lecture, Lab}
• Transceivers - Describes the advancements and features of Spartan UltraScale+ transceivers compared to previous UltraScale architectures. {Lecture}
• Transceivers Wizard - Reviews the functionality and benefits of the transceiver wizard. {Lecture}
• PCI Express® -  Discusses the architecture of the PCIe blocks in the Spartan UltraScale+ device and the differences between the different PCIe blocks. {Lecture}
• Configuration - Provides an overview of the configuration process for Spartan UltraScale+ FPGAs. {Lecture}
• Security Features - Describes the platform security framework offered by Spartan UltraScale+ devices. Also identifies the available advanced
  security features. {Lecture}
• Power Design Manager - Explores the power estimation tools and how to utilize them for achieving better power efficiency using PDM. {Lecture, Lab}
• Power Analysis and Optimization Using the AMD Vivado - Design Suite Describes how to estimate and analyze power consumption with the AMD Vivado Design Suite Power Report utility. {Lecture}