Designing with Dynamic Function eXchange
(DFX) Using the Vivado Design Suite

Course Description

Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite. This course covers both the tool flow and mechanics of successfully creating a DFX design.


The emphasis of this course is on:

  • Identifying best design practices and understanding the subtleties of the DFX design flow
  • Using the DFX Controller and DFX Decoupler IP in the DFX process
  • Implementing DFX in an embedded system environment
  • Applying appropriate debugging techniques on DFX designs
  • Employing best practice coding styles for a DFX system



Training Duration

2 days


Digital designers who have a working knowledge of HDL (VHDL or Verilog) and the Xilinx design methodology and who have need to understand Dynamic Function eXchange techniques.


Software Tools

  • Vivado Design Suite 2022.2
  • Vitis™ unified software platform 2022.2


  • Demo board: Zynq® UltraScale+™ MPSoC ZCU104 board*

       *  Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.


Skills Gained

After completing this comprehensive training, you will know how to:

  • Describe what Dynamic Function eXchange is
  • Define DFX regions and Reconfigurable Modules with theVivado® Design Suite
  • Generate the appropriate full and partial bitstreams for a DFX design
  • Implement a nested DFX design
  • Use the ICAP and PCAP components to deliver the partially reconfigurable systems
  • Implement a DFX system using the DFX Controller IP
  • Identify how Dynamic Function eXchange affects various silicon resources, including block RAM, IOBs, fabric, and MGTs
  • Implement a Dynamic Function eXchange system using the following techniques
  • Direct JTAG connection, floorplanning, and timing constraints and analysis
  • Debug a DFX designs using the Vivado Design Suite
  • Implement a DFX system in an embedded environment using the Vitis IDE s

Course Outline

Day 1

  •  Introduction to Dynamic Function eXchange (DFX)Explains what Dynamic Function eXchange is and defines the terminologies used in DFX. Also provides an overview of the configuration and reconfiguration processes. {Lecture, Demo}
  • DFX Flow Using the Vivado Design Suite GUIIllustrates the steps for creating a DFX project in the Vivado Design Suite and describes various supported and unsupported features. {Lecture, Lab}
  • DFX Flow Using Vivado Design Suite Tcl CommandsReviews the flow using nonprojectbased commands, including using implementation constraints and specific characteristics. {Lecture, Lab}
  • Nested DFXDescribes using nested DFX, the process by which a Reconfigurable Partition (RP) can be segmented into smaller regions, each of which is partially reconfigurable. {Lecture, Lab}
  • Abstract Shell for Dynamic Function eXchange  – Describes how compilation time can be reduced by using an Abstract shell (UltraScale+ devices only). {Lecture}
  • DFX Design Considerations for All AMD DevicesCovers the requirements, characteristics, and limitations associated with DFX designs that can simplify the debug process and reduce the risk of design malfunctions. {Lecture}
  • DFX Design Considerations for 7 Series, Zynq SoC, UltraScale, and UltraScale+ DevicesDiscusses DFX design consideration methodologies for various  Xilinx device families. {Lecture}
  • DFX Design Considerations for Versal DevicesDescribes the DFX design requirements that are specific to Versal devices. {Lecture}
  • DFX Intellectual Property (IP)Reviews the various IPs that are specifically for use with with DFX designs. {Lecture, Lab, Demo}
  • DFX Block Design Containers in IP Integrator – Describes the block design container feature and how BDCs enable DFX. {Lecture, Lab}

Day 2

  • Configuring Devices Using DFXReviews the basics of configuration and various configuration modes. {Lecture}
  • Configuration ParametersCovers various configuration parameters, including factors that affect configuration time and configuration debugging. {Lecture}
  • DFX BitstreamsDescribes the different types of bitstreams for DFX compilation, including full, partial, blanking, and clearing. {Lecture}
  • DFX Bitstream IntegrityDescribes partial bit file integrity and implementing DFX through the ICAP for FPGA devices. {Lecture}
  • Floorplanning a DFX DesignDemonstrates how to create Pblocks for various devices and how to create a floorplan for a reconfigurable region. {Lecture, Lab}
  • DFX Timing Analysis and ConstraintsIllustrates how and when to apply different constraint files, the process of performing a DFX timinglevel simulation, and the process of performing static timing analysis on a DFX design. {Lecture, Lab}
  • DFX DebuggingIllustrates DFX debugging techniques using Vivado Design Suite debug cores. {Lecture, Lab}
  • DFX in Embedded Systems  –Describes the embedded design flow in the Vivado Design Suite, the advantages of using a processor with DFX, and how to connect a processor to the PCAP to control DFX using the Vitis IDE. {Lecture, Lab}
  • DFX Designs Using the PCIe CoreReviews the advantages of using a PCIe core in a DFX design. {Lecture}



04 september 2023 - 05 september 2023

Cereslaan 24
5384 VT

€ 0,00
20 Xilinx Training Credits

Training brochure


Registratie op aanvraag, neem contact op met ons.