Designing with the UltraScale and UltraScale+ Architectures

Course Description

This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale™ and UltraScale+ architectures. Targeted towards designers who have used the Vivado® Design Suite, this course focuses on designing for the new and enhanced resources found in our new FPGA families. Topics covered include an introduction to the UltraScale architecture CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources.

A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered. In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.

xilinxultrascalefamilyLevel

FPGA 3

Training Duration

2 days

Who Should Attend?

Anyone who would like to build a design for the UltraScale or UltraScale+ device family

Prerequisites

Software Tools

  • Vivado System Edition 2016.3

Hardware

  • Architecture: UltraScale and UltraScale+ FPGAs*
  • Demo board: None*

* This course focuses on the UltraScale and UltraScale+ architectures. Check with your local Authorized Training Provider for specifics or other customizations

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Take advantage of the primary UltraScale architecture resources
  • Describe the new CLB capabilities and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO, and DSP resources available
  • Describe the UltraRAM features
  • Properly design for the I/O and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included
  • Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible

Course Outline

Day 1

  • Introduction to the UltraScale Architecture {Lecture}
  • UltraScale Architecture CLB Resources {Lecture, Lab}
  • HDL Coding Techniques {Lecture, Lab}
  • UltraScale Architecture Clocking Resources {Lectures, Lab}
  • FPGA Design Migration {Lecture, Lab}
  • Clocking Migration {Lab}
  • UltraScale Architecture Block RAM Memory Resources {Lecture}
  • UltraScale Architecture FIFO Memory Resources {Lecture}
  • UltraRAM Memory {Lecture, Lab}
  • UltraScale Architecture DSP Resources {Lecture}

Day 2

  • Design Migration Software Recommendations {Lecture}
  • DDR3 MIG Design Migration {Lab}
  • DDR4 Design Creation Using MIG {Lab}
  • UltraScale Architecture I/O Resources Overview {Lecture}
  • UltraScale Architecture I/O Resources – Component Mode {Lecture, Lab}
  • UltraScale Architecture I/O Resources – Native Mode {Lecture, Lab}
  • Design Migration Methodology {Lecture}
  • 10G PCS/PMA and MAC Design Migration {Lab}
  • UltraScale Architecture Transceivers {Lecture, Lab}
  • UltraScale FPGAs Transceivers Wizard {Lecture, Lab, Demo}
  • Introduction to the UltraScale+ Families {Lecture}

Topic Descriptions

Day 1

  • UltraFast Design Methodology Introduction 2 – Overview of the methodology guidelines covered in this course.
  • Scripting in a Vivado Design Suite Project-Based Flow. – Explains how to write Tcl commands in the project-based flow for a design.
  • Clocking Resources – Describes various clock resources, clocking layout, and routing in a design.
  • Synchronous Design Techniques – Introduces synchronous design techniques used in an FPGA design.
  • Register Duplication – Use register duplication to reduce high fanout nets in a design.
  • Resets – Investigates the impact of using asynchronous resets in a design.
  • I/O Logic Resources – Overview of I/O resources and the IOB property for timing closure.
  • Timing Summary Report – Use the post-implementation timing summary report to sign-off criteria for timing closure.
  • Introduction to Timing Exceptions – Introduces timing exception constraints and applying them to fine tune design timing.

Day 2

  • Generated Clocks – Use the report clock networks report to determine if there are any generated clocks in a design.
  • Applying Clock Groups Constraints – Apply clock groups constraint for asynchronous clock domains.
  • Creating and Packaging Custom IP – Create your own IP and package and include it in the Vivado IP catalog.
  • Using an IP Container – Use a core container file as a single file representation for an IP.
  • Designing with IP Integrator – Use the Vivado IP integrator to create the uart_led sub-system.
  • Introduction to the HLx Design Flow.– Use the HLx design flow to increase productivity and reduce run time when designing and verifying a design.
  • Configuration Process – Understand the FPGA configuration process, such as device power up, CRC check, etc.
  • Sampling and Capturing Data in Multiple Clock Domains in VLA.– Overview of debugging a design with multiple clock domains that require multiple ILAs.
  • Design Analysis Using Tcl Data Structures – Analyze a design using Tcl commands.
  • Power Analysis and Optimization Using the Vivado Design Suite – Use report power commands to estimate power consumption.

Vivado


Datum
11 april 2017 - 12 april 2017

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.450,00
of
18 Xilinx Training Credits

Informatie
Training brochure

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