Designing FPGAs Using the Vivado Design Suite 4

Course Description

Learn how to use the advanced aspects of the Vivado® Design Suite and AMD Xilinx hardware.
The focus is on:

  • Applying timing constraints for sourcesynchronous and systemsynchronous interfaces
  • Utilizing floorplanning techniques
  • Employing advanced implementation options
  • Utilizing AMD Xilinx security features
  • Identifying advanced FPGA configurations
  • Debugging a design at the device startup phase
  • Using Tcl scripting in nonproject batch flows

This is the final course in the Designing FPGAs Using the Vivado Design Suite series.

PrintLevels

FPGA 4

Course Duration

2 days

Audience

Engineers who seek advanced training in using Xilinx tools to improve FPGA performance and utilization while also increasing productivity.

Prerequisites

Software Tools

  • Vivado Design Suite 2022.2

Hardware

  • Architecture: UltraScale™ FPGAs and Versal® ACAPs*
  • Demo board: Zynq® UltraScale+™ ZCU104 board*

* This course focuses on the UltraScale and Versal architectures. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Analyze a timing report to identify how to center the clock in the data eye
  • Apply appropriate techniques to reduce logic and net delay and to improve clock skew and clock uncertainty
  • Implement Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
  • Utilize floorplanning techniques to improve design performance
  • Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
  • Utilize security features, bitstream encryption, and authentication using AES for design and IP security
  • Identify advanced FPGA configurations, such as daisy chain and gangs, for configuring multiple FPGAs in a design
  • Debug a design at the device startup phase to debug issues related to startup events, .such as MMCM lock and design coming out of reset
  • Use Tcl scripting in non-project batch flows to synthesize, implement, and generate custom timing reports

Course Outline

Day 1

  • Introduction to UltraFast Design Methodology Design Closure Introduces the UltraFast methodology guidelines on design closure. {Lecture}
  • Hierarchical Design Overview of the hierarchical design flows in the Vivado Design Suite. {Lecture}
  • Incremental Compile Flow Utilize the incremental compile flow when making lastminute RTL changes. {Lecture, Lab}
  • Vivado Design Suite ECO Flow Use the ECO flow to make changes to a previously implemented design and apply changes to the original design. {Lecture, Lab}
  • Managing IP in Remote Locations Store IP and related files remote to the current working project directory. {Lecture, L
  • Timing Closure Using Physical Optimization Techniques Use physical optimization techniques for timing closure. {Lecture, Lab}
  • Case Analysis Understand how to analyze timing when using multiplexed clocks in a design. {Lecture}
  • Reducing Logic Delay Describes how to optimize regular fabric paths and paths with  dedicated blocks and macro primitives. {Lecture}
  • Reducing Net Delay Reviews different techniques to reduce congestion and net delay. {Lecture}
  • Improving Clock Skew Describes how to apply various techniques to improve clock skew. {Lecture}
  • Improving Clock Uncertainty Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab}
  • Intelligent Design Runs (IDR)Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to
    close timing. {Lecture, Lab}

Day 2

  • Introduction to Floorplanning Introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
  • Design Analysis and Floorplanning Explore the pre and postimplementation design analysis features of the Vivado IDE. {Lecture, Lab}
  • Congestion Identifies congestion and addresses congestion issues. {Lecture}
  • Power Management Techniques Identify techniques used for low power design. {Lecture}
  • Versal ACAP: Power Management Discusses power domains and how they can be controlled along with basic techniques used to lower overall power consumption. {Lectur
  • Daisy Chains and Gangs in Configuration Introduces advanced configuration schemes for multiple FPGAs. {Lecture}
  • Bitstream Security Understand the AMD Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication. {Lecture, Demo}
  • Vivado Design Suite Debug Methodology Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}
  • Trigger and Debug at Device Startup Debug the events around the device startup. {Lecture, Demo}
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer. {Lecture, Lab}
  • Versal ACAP: Debugging Covers the Versal ACAP debug interfaces, such as the test access port (TAP), debug access port (DAP) controller, and highspeed debug port (HSDP). {Lecture, Lab}
  • Introduction to the Vivado Store Introduces the Xilinx Vivado Store. {Lecture, Demo}
  • Scripting in Vivado Design Suite NonProject Mode Write Tcl commands in the nonproject batch flow for a design. {Lecture, Lab}
  • Debugging the Design Using Tcl Commands Use Tcl scripting for VLA designs for adding probes and making connections to probes. {Lecture, Lab}
  • Using Procedures in Tcl Scripting Employ procedures in Tcl scripting. {Lecture}
  • Using Lists in Tcl Scripting Employ lists in Tcl scripting. {Lecture}
  • Debugging and Error Handling in Tcl Scripts Understand how to debug errors in a Tcl script. {Lecture}

 

FPGA


Datum
08 november 2023 - 09 november 2023

Locatie
Core|Vision
Cereslaan 24
5384 VT
Heesch

Prijs
€ 0,00
of
20 Xilinx Training Credits

Informatie
Training brochure

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