Designing FPGAs Using the Vivado Design Suite 4

This is the final course in the Designing FPGAs Using the Vivado Design Suite series.

Levels

FPGA 4

Course Duration

2 days.

Audience

Prerequisites

• Intermediate HDL knowledge (Verilog or VHDL).
• Sound digital design background.
• Designing FPGAs Using the Vivado Design Suite 1 course
• Designing FPGAs Using the Vivado Design Suite 2 course
• Designing FPGAs Using the Vivado Design Suite 3 course

Software Tools

• Vivado Design Suite 2024.1

Hardware

• Architecture: UltraScale™ FPGAs*
• Demo board: Zynq® UltraScale+™ ZCU104 board*

* This course focuses on the UltraScale architectures. Check with your local Authorized Training Provider for specifics or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Analyze a timing report to identify how to center the clock in the data eye
• Apply appropriate techniques to reduce logic and net delay and to improve clock skew and clock uncertainty
• Implement Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
• Utilize floorplanning techniques to improve design performance
• Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
• Utilize security features, bitstream encryption, and authentication using AES for design and IP security
• Identify advanced FPGA configurations, such as daisy chain and gangs, for configuring multiple FPGAs in a design
• Debug a design at the device startup phase to debug issues related to startup events, .such as MMCM lock and design coming out of reset
• Utilize Tcl scripting when using the Vivado logic analyzer in a designs

Course Outline

Day 1

• UltraFast Design Methodology: Timing Closure – Introduces the UltraFast methodology guidelines on design closure. {Lecture}
• Hierarchical Design Overview of the hierarchical design flows in the Vivado Design Suite. {Lecture}
• Incremental Compile Flow Utilize the incremental compile flow when making last–minute RTL changes. {Lecture, Lab}
• Vivado Design Suite ECO Flow Use the ECO flow to make changes to a previously implemented design and apply changes to the original design. {Lecture, Lab}
  
• Managing IP in Remote Locations Store IP and related files remote to the current working project directory. {Lecture, L
  
• Timing Closure Using Physical Optimization Techniques Use physical optimization techniques for timing closure. {Lecture, Lab}
• Reducing Logic Delay Describes how to optimize regular fabric paths and paths with  dedicated blocks and macro primitives. {Lecture}
  
• Reducing Net Delay Reviews different techniques to reduce congestion and net delay. {Lecture}
• Improving Clock Skew Describes how to apply various techniques to improve clock skew. {Lecture}
• Improving Clock Uncertainty Reviews various flows for improving clock uncertainty, including using parallel BUFGCE_DIV clock buffers, changing MMCM or PLL settings, and limiting synchronous clock domain crossing (CDC) paths. {Lecture, Lab}
• Intelligent Design Runs (IDR) – Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}
• Power Management Techniques – Describes the techniques used for low power design. {Lecture}

Day 2

• Introduction to Floorplanning Introduction to floorplanning and how to use Pblocks while floorplanning. {Lecture}
• Design Analysis and Floorplanning Explore the pre– and post–implementation design analysis features of the Vivado IDE. {Lecture, Lab}
• Congestion Identifies congestion and addresses congestion issues. {Lecture}
• Daisy Chains and Gangs in Configuration Introduces advanced configuration schemes for multiple FPGAs. {Lecture}
• Bitstream Security Understand the AMD Xilinx bitstream security features such as readback disable, bitstream encryption, and authentication. {Lecture, Demo}
• Vivado Design Suite Debug Methodology Understand and follow the debug core recommendations. Employ the debug methodology for debugging a design using the Vivado logic analyzer. {Lecture}
• Trigger and Debug at Device Startup Debug the events around the device startup. {Lecture, Demo}
• Trigger Using the Trigger State Machine in the Vivado Logic Analyzer Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer. {Lecture, Lab}
  
• Introduction to the Vivado Store Introduces the Xilinx Vivado Store. {Lecture, Demo}
• Scripting in Vivado Design Suite Non–Project Mode Write Tcl commands in the non–project batch flow for a design. {Lecture, Lab}
• Debugging the Design Using Tcl Commands Use Tcl scripting for VLA designs for adding probes and making connections to probes. {Lecture, Lab}
• Using Procedures in Tcl Scripting Employ procedures in Tcl scripting. {Lecture}
• Using Lists in Tcl Scripting Employ lists in Tcl scripting. {Lecture}
• Debugging and Error Handling in Tcl Scripts Understand how to debug errors in a Tcl script. {Lecture}