Designing FPGAs Using the Vivado Design Suite 3

Course Description

This course demonstrates timing closure techniques, such as baselining,.pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.

PrintLevel

FPGA 3

Course Duration

2 days

Audience

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite.

This course builds further on the previous Designing FPGAs Using the Vivado Design Suitecourses

Prerequisites

Optional  Videos

Software Tools

  • Vivado System Edition 2020.1

Hardware

  • Architecture: UltraScale™ family*
  • Demo board board: Zynq® UltraScale+™ ZCU104 board*

* This course focuses on the UltraScale architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

  • Employ good alternative design practices to improve design reliability
  • Define a properly constrained design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
  • Build a more reliable design that is less vulnerable to metastability problems. and requires less design debugging later in the development cycle
  • Increase performance by utilizing FPGA design techniques
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
  • Identify timing closure techniques using the Vivado Design Suite

Course Outline

Day 1

  • UltraFast Design Methodology: Implementation {Lecture}
  • Vivado Design Suite Non-Project Mode {Lecture}
  • Baselining {Lecture, Lab, Demo}
  • Pipelining {Lecture, Lab}
  • Inference {Lecture, Lab}
  • Revision Control Systems in the Vivado Design Suite {Lecture, Lab}
  • Timing Simulation {Lecture, Lab}
  • Synchronization Circuits {Lecture, Demo}

Day 2

  • Report Clock Interaction {Lecture, Demo}
  • Report Data Sheet {Lecture, Demo}
  • Report QoR {Lecture}
  • Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab}
  • Configuration Modes {Lecture}
  • Netlist Insertion Debug Probing Flow {Lecture, Lab}
  • Samploing and Capturing Data in Multiple Clock Domains {Lecture, Lab}
  • JTAG-to-AXI-Master Core {Lecture, Demo}
  • Debug Flow in an IP Integrator Block Design {Lecture, Lab}
  • Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab}
  • Manipulate Design Properties Using Tcl {Lecture, Lab}

Topic Descriptions

Day 1

  • UltraFast Design Methodology Implementation – Introduces the methodology guidelines covered in this course.
  • Vivado Design Suite Non-Project Mode – Create a design in the Vivado Design Suite non-project mode.
  • Baselining – Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  • Pipelining – Use pipelining to improve design performance.
  • Inference – Infer xilinx dedicated hardware resources by writing appropriate HDL code.
  • Revision Control Systems in the Vivado Design Suite – Use version control systems with Vivado design flows.
  • Timing Simulation – Simulate the design post-implementation to verify that a design works properly on hardware.
  • Synchronization Circuits – Use synchronization circuits for clock domain crossings.

Day 2

  • Report Clock Interaction – Use the clock interaction report to identify interactions between clock domains.
  • Report Data Sheet – Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
  • Report QoR – Use the QoR Assessment and QoR Suggestions reports to analyze the timing for a design.
  • Dynamic Power Estimation Using Vivado Report Power.– Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
  • Configuration Modes – Understand various configuration modes and select the suitable mode for a design.
  • Netlist Insertion Debug Probing Flow – Covers the netlist insertion flow of the debug using the Vivado logic analyzer
  • Sampling and Capturing Datain Multiple Clock Domains.– Overview of debugging a design with multiple clock domains that require multiple ILAs
  • JTAG-to-AXI-Master Core. – Use this debug core to write/read data to/from a peripheral connected to an AXI interface.
  • Debug Flow in an IP Integrator Block Design – Insert the debug cores into IP integrator block designs.
  • Remote Debugging Using the Vivado Logic Analyzer.– Use the Vivado logic analyzer to configure an FPGA, set up triggering,.and view the sampled data from a remote location.
  • Manipulate Design Properties Using Tcl – Query your design and make pin assignments using various Tcl commands.


Datum
21 september 2020 - 22 september 2020

Locatie
On Request


Online or Heesch

Prijs
€ 1.650,00
of
20 Xilinx Training Credits

Informatie
Training brochure

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