Xilinx – Designing an Integrated PCI Express System ONLINE
PLEASE NOTE: This is a LIVE INSTRUCTOR-LED training event delivered ONLINE.
It covers the same scope and content, and delivers similar learning outcomes, as a scheduled face-to face class.
Attending this course will provide students a working knowledge of how to implement a Xilinx PCI Express® core in custom applications. This course offers students hands-on experience with implementing a Xilinx PCI Express system within the customer education reference design. With this experience, users can improve their time to market with the PCIe core design. Various Xilinx PCI Express core products will be enumerated to aid in selecting the proper solution. This course focuses on the AXI streaming interconnect.
Who Should Attend?
- Hardware designers who want to create applications using Xilinx IP cores for PCI Express
- Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
- System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications.
- Experience with PCIe specification protocol
- Knowledge of VHDL or Verilog
- Some experience with Xilinx implementation tools
- Some experience with a simulation tool, preferably the VivadoÂ® simulator
- Moderate digital design experience
- Vivado™ Design or System Edition 2017.1
- Architecture: UltraScale/UltraScale+ and 7 series FPGAs*
- Demo board: KintexUltraScale FPGA KCU105 board or Kingtex-7 FPGA KC705 board*
After completing this comprehensive training, you will know how to:
- Construct a basic PCIe system by:
- Selecting the appropriate core for your application
- Specifying requirements of an endpoint application
- Connecting this endpoint with the core
- Utilizing FPGA resources to support the core
- Simulating the design
- Identify the advanced capabilities of the PCIe specification protocol and feature set
- Course Introduction
- Xilinx PCI Express Solutions
- Connecting Logic to the Core â€“ AXI Interface
- PCIe Core Customization
- Lab 0: Packet Coding
This lab helps you recall basic PCI Express transaction layer packet formats
- Lab 1: Constructing the PCIe Core
This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
- Packet Formatting Details
- Simulating a PCIe System Design
- Endpoint Application Considerations
- Lab 2: Simulating the PCIe Core
This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets
- PCI Express in Embedded Systems
- Application Focus: DMA
- Design Implementation and PCIe Configuration
- Lab 3: Using the PCI Express Core in IP Integrator
This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design
- Root Port Applications
- Debugging and Compliance
- Interrupts and Error Management
- Course Summary
- Lab 4: Implementing the PCIe Design
This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode.
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27 april 2020 - 30 april 2020
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28 Xilinx Training Credits
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