4 sessions (Details » )

• Hardware designers who want to create applications using Xilinx IP cores for PCI Express
• Software engineers who want to understand the deeper workings of the Xilinx PCI Express solution
• System architects who want to leverage key Xilinx advantages related to performance, latency, and bandwidth in PCI Express applications.

• Experience with PCIe specification protocol
• Knowledge of VHDL or Verilog
• Some experience with Xilinx implementation tools
• Some experience with a simulation tool, preferably the Vivado® simulator
• Moderate digital design experience

• Vivado™ Design or System Edition 2014.3

• Architecture: 7 series FPGAs*
• Demo board: None*

* This course focuses on the 7 series architecture. Please contact Doulos for the specifics or other customizations.

After completing this comprehensive training, you will know how to:

• Construct a basic PCIe system by:
  • Selecting the appropriate core for your application
  • Specifying requirements of an endpoint application
  • Connecting this endpoint with the core
  • Utilizing FPGA resources to support the core
  • Simulating the design
• Identify the advanced capabilities of the PCIe specification protocol and feature set

• Introduction to the PCIe Architecture
• Review of the PCIe Protocol
• PCIe Core Customization
• Lab 1: Constructing the PCIe Core
• Simulating a PCIe System Design
• Connecting Logic to the Core – AXI Interface
• Packet Formatting Details
• Lab 2: Downstream Port Model Simulation

• Endpoint Application Considerations
• Lab 3: Pseudo-Transactional Modeling
• Application Focus: DMA
• Lab 4: Design Implementation
• 7 Series Root Port
• PCIe Configuration
• Compliance and Debugging
• Lab 5: Debugging the PCIe Core with the Vivado Logic Analyzer**
• Interrupts and Error Management
• Appendix: Mechanicals, Hot Plug, and Power
• Appendix: 7 Series Gen3 PCIe Core Solutions

**Will be available in a future release.

• Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
• Lab 2: Downstream Port Model Simulation – This lab demonstrates how timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture the effects of link training and write packets to the endpoint application for later use.
• Lab 3: Pseudo-Transactional Modeling – This lab illustrates pseudo-transactional modeling, which provides various packets to the user design without the need to simulate the PCIe cores themselves.
• Lab 4: Design Implementation – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream.
• Lab 5: Debugging the PCIe Core with the Vivado Logic Analyzer** – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.