BEGIN:VCALENDAR VERSION:2.0 PRODID:-//wp-events-plugin.com//7.2.3.1//EN TZID:Europe/Amsterdam X-WR-TIMEZONE:Europe/Amsterdam BEGIN:VEVENT UID:755@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20300101T091500 DTEND;TZID=Europe/Amsterdam:20300101T092000 DTSTAMP:20260212T103922Z URL:https://www.core-vision.nl/events/designing-fpgas-using-the-vivado-des ign-suite-1-4/ SUMMARY:Designing FPGAs Using the Vivado Design Suite 1 DESCRIPTION:Course Description\nThis course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flo w.\n\nThe course provides experience with:\n\n Creating a Vivado Design S uite project with source files.\n Simulating a design.\n Performing pin assignments.\n Applying basic timing constraints.\n Synthesizing and imp lementing.\n Debugging a design.\n Generating and downloading a bitstrea m onto a demo board.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpga-vdes2-e1718949197527.png END:VEVENT BEGIN:VEVENT UID:610@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250910T090000 DTEND;TZID=Europe/Amsterdam:20250911T170000 DTSTAMP:20250904T065914Z URL:https://www.core-vision.nl/events/essential-dsp-implementation-techniq ues-for-xilinx-fpgas-3/ SUMMARY:Essential DSP Implementation Techniques for Xilinx FPGAs ✅ DESCRIPTION:✅ indicates CONFIRMED TO RUN courses\nCourse Description\nThi s course provides a foundation for Digital Signal Processing (DSP) techniq ues for Xilinx FPGAs. The course begins with a refresher of basic binary number theory\, mathematics\, and the essential features within the FPGA t hat are important to signal processing. The body of the course explores a variety of filter techniques with emphasis on optimal implementation in X ilinx devices and continues with an examination of FFTs\, video\, and imag e processing. Throughout the course\, Xilinx cores and IP relevant to sig nal processing are introduced. The course is complemented by hands-on exer cises to reinforce the concepts learned.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/06/shutterstock_136710647-e1718948748220.jpg CATEGORIES:AMD,DSP,FPGA,KRIA,ML,On Request,Vision LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:608@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250912T090000 DTEND;TZID=Europe/Amsterdam:20250912T170000 DTSTAMP:20250731T044052Z URL:https://www.core-vision.nl/events/migrating-to-the-vitis-embedded-soft ware-development-ide-6/ SUMMARY:Migrating to the Vitis Embedded Software Development IDE DESCRIPTION:Course Description\n\n\nThis course demonstrates the tools and techniques required for embedded software design and development using the AMD Vitis™ Unified IDE.The emphasis of this course is on:\n\n Reviewin g the basics of the embedded software development flow\n Exploring the te rminology and features of the Vitis Unified IDE\n Developing bare-metal a nd Linux® applications\n Debugging applications using the Vitis Unified IDE\n Using the Vitis Python™ command line interface\n Migrating from the classic Vitis IDE to the Vitis Unified IDE\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/idirect-code-e1718949899167.webp CATEGORIES:Embedded,FPGA,MicroBlaze,MPSoC,System,Versal,Vitis,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:588@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250915T090000 DTEND;TZID=Europe/Amsterdam:20250919T170000 DTSTAMP:20250731T044249Z URL:https://www.core-vision.nl/events/expert-vhdl-5/ SUMMARY:Expert VHDL DESCRIPTION:Course Description\nExpert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase productivity by en hancing their knowledge of the VHDL language itself and its application fo r design and verification. Presented in two distinct course modules\, Expe rt VHDL focuses on language and synthesis issues\, design maintainability and re-use\, structured verification environments and the latest technique s for verification - including an introduction to OVL/PSL and introduction s to OSVVM and UVVM.\n\n Expert VHDL Design (2 days) is for design engine ers wishing to deepen their knowledge of RTL synthesis using VHDL\, and to improve their VHDL coding style with design maintainability and re-use in mind. This section also includes the introduction to OVL/PSL.\n Expert V HDL Verification (3 days) is for design engineers and verification enginee rs involved in VHDL test bench development or behavioural modelling for th e purpose of functional verification. Advanced VHDL language constructs ar e presented using a practical testbench methodology as an example. The alt ernative OSVVM and UVVM methodologies are then introduced and all three me thodologies compared and contrasted.\n\nThe modules\, which may be attende d together or independently\, follow on from the industry standard class\, Comprehensive VHDL. Carefully designed workshops comprise approximately 5 0% of teaching time\,.and enable engineers to apply their new skills in th e context of the latest VHDL design tools\, practices and methodologies.\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/scripting.jpg CATEGORIES:Doulos,VHDL LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:590@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250915T090000 DTEND;TZID=Europe/Amsterdam:20250916T170000 DTSTAMP:20250731T043028Z URL:https://www.core-vision.nl/events/expert-vhdl-design-5/ SUMMARY:Expert VHDL Design DESCRIPTION:Course Description\nExpert VHDL Design is a 2 days class part o f the intensive 5-day Expert VHDL class.\n\n Expert VHDL Design (2 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL\, and to improve their VHDL coding style with design maintaina bility and re-use in mind. This section also includes the introduction to OVL/PSL.\n\nThe modules\, which may be attended together or independently\ , follow on from the industry standard class\, Comprehensive VHDL. Careful ly designed workshops comprise approximately 50% of teaching time\, and en able engineers to apply their new skills in the context of the latest VHDL design tools\, practices and methodologies.\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/scripting.jpg CATEGORIES:Doulos,VHDL LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:596@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250922T090000 DTEND;TZID=Europe/Amsterdam:20250923T170000 DTSTAMP:20250915T053742Z URL:https://www.core-vision.nl/events/embedded-heterogeneous-design-6/ SUMMARY:Embedded Heterogeneous Design ✅ DESCRIPTION:✅ indicates CONFIRMED TO RUN courses\nCourse Description\nThi s course covers the AMD Versal™ architecture and illustrates the tool fl ow for developing HLS and AI Engine components as well as integrating an e ntire system project to design an embedded heterogeneous system using the v++ tools and AMD Vitis™ Unified IDE.The emphasis is on:\n\n Describing an embedded heterogeneous system design\n Illustrating the AMD Versal ad aptive SoC architecture\, NoC\, and AI Engine\n Describing an AMD Versal design tool flow\n Developing HLS and AIE components using the AMD Vitis tool\n Utilizing the v++ command line tools for component compilation\, l inking\, and packaging to run emulation\n Demonstrating the system design flow for a heterogeneous embedded system using the AMD Vitis Unified IDE\ n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/08/versal-workshop-2024-take-2.jpg CATEGORIES:AMD,Embedded,FPGA,KRIA,MPSoC,Versal,Vitis,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:594@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250922T090000 DTEND;TZID=Europe/Amsterdam:20250923T170000 DTSTAMP:20250731T044508Z URL:https://www.core-vision.nl/events/embedded-systems-design-5/ SUMMARY:Embedded Systems Design DESCRIPTION:Course Description\nLearn general embedded concepts\, tools\, a nd techniques using the AMD Vivado™ Design Suite and AMD Vitis™ Unifie d IDE.The emphasis is on:\n\n Designing\, expanding\, and modifying embed ded systems utilizing the features and capabilities of the Zynq™ System on a Chip (SoC)\, Zynq UltraScale+™ MPSoC\, Versal™ adaptive SoC\, and MicroBlaze™ V soft processor\n Adding and simulating AXI-based periphe rals using bus functional model (BFM) simulation\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/embedded3-e1718948872404.webp CATEGORIES:AMD,Embedded,FPGA,KRIA,MicroBlaze,MPSoC,Versal,Vitis,Vivado,Zyn q LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:606@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250924T090000 DTEND;TZID=Europe/Amsterdam:20250926T170000 DTSTAMP:20250630T051443Z URL:https://www.core-vision.nl/events/embedded-systems-software-design-4/ SUMMARY:Embedded Systems Software Design DESCRIPTION:Course Description\nhis course introduces the concepts\, tools\ , and techniques required for software design and development for the AMD Zynq™ System on a Chip (SoC)\, Zynq UltraScale+™ MPSoC\, and Versal™ adaptive SoC architectures using the AMD Vitis™ Unified IDE.\nThe focus is on:\n\n Reviewing the basics of Vitis Unified IDE\n Customizing boar d support packages (BSPs) for resource access and management of the Xilinx Standalone library\n Utilizing device drivers effectively\n Developing software applications for the available processors\n Debugging and integr ating user applications\n Employing best practices to enable good design decisions\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/idirect-code-e1718949899167.webp CATEGORIES:AMD,Embedded,FPGA,KRIA,MPSoC,Versal,Vitis,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:831@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20300101T153000 DTEND;TZID=Europe/Amsterdam:20300101T153500 DTSTAMP:20251202T082441Z URL:https://www.core-vision.nl/events/essential-digital-design-techniques- 5/ SUMMARY:Essential Digital Design Techniques DESCRIPTION:Course Description\nEssential Digital Design Techniques is a fa st-track\,.application orientated course designed to bridge the gap betwee n text book theory and real world digital design practice.\nIt significant ly accelerates the on-the-job learning curve for engineers new to digital design\,.or those needing to refine their design skills before project inv olvement. With a strong emphasis on practical design and hands-on workshop s\,.this course has been specifically developed to capture design techniqu es usually learned over months\, in an intensive 2-day format.\nEssential Digital Design Techniques provides the ideal first stage in full scale pro ject training for graduate design engineers\,.or engineers moving into dig ital design from other disciplines (including software or analog design). As such\, it is the natural precursor to the Doulos Comprehensive VHDL and Comprehensive Verilog courses\,.which prepare engineers for HDL applicati on within FPGA or ASIC design projects.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/embedded-systemen-corevision.webp CATEGORIES:Digital Design,Doulos,FPGA,Hardware,On Request,VHDL END:VEVENT BEGIN:VEVENT UID:602@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250929T090000 DTEND;TZID=Europe/Amsterdam:20250930T170000 DTSTAMP:20250731T044716Z URL:https://www.core-vision.nl/events/adaptive-socs-for-system-architects- 4/ SUMMARY:Adaptive SoCs for System Architects DESCRIPTION:Course Description\nThis course provides system architects with an overview of the capabilities and support for the AMD Zynq™ UltraScal e+™ MPSoC and Versal™ adaptive SoC devices.The emphasis is on:\n\n \n \n Utilizing power management strategies effectively\n Leveraging the pl atform management unit (PMU) capabilities\n Running the system securely a nd safely\n Reviewing the high-level architecture of the devices\n Ident ifying appropriate boot sequences\n\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/embedded3-e1718948872404.webp CATEGORIES:AMD,Embedded,FPGA,KRIA,MPSoC,System,Vitis,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:604@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20250929T090000 DTEND;TZID=Europe/Amsterdam:20250930T170000 DTSTAMP:20250731T044816Z URL:https://www.core-vision.nl/events/zynq-ultrascale-mpsoc-for-the-hardwa re-designer-6/ SUMMARY:Zynq UltraScale+ MPSoC for the Hardware Designer DESCRIPTION:Course Description\nThis course provides hardware designers wit h an overview of the capabilities and support for the Zynq® UltraScale+ ™ MPSoC family from a hardware architectural perspective.The emphasis is on:\n\n Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)\n Reviewing the various power d omains and their control structure\n Illustrating the processing system ( PS) and programmable logic (PL) connectivity\n Utilizing QEMU to emulate hardware behavior\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/08/MPSoC-e1725463185155.jpg CATEGORIES:AMD,Embedded,FPGA,MPSoC,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:598@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251001T090000 DTEND;TZID=Europe/Amsterdam:20251002T170000 DTSTAMP:20250731T044936Z URL:https://www.core-vision.nl/events/zynq-ultrascale-mpsoc-boot-and-platf orm-management-5/ SUMMARY:Zynq UltraScale+ MPSoC: Boot and Platform Management DESCRIPTION:Course Description\nThis course provides software developers re sponsible for booting and platform management with an overview of the capa bilities and support for the AMD Zynq™ UltraScale+™ MPSoC\n\nThe empha sis is on:\n\n Reviewing the catalog of OS implementation options\, inclu ding hypervisors and various Linux® implementations\n Booting and config uring a system\n Applying various power management techniques for the Zyn q UltraScale+ MPSoC\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/idirect-code-e1718949899167.webp CATEGORIES:AMD,Embedded,FPGA,KRIA,MPSoC,Versal,Vitis,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:600@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251001T090000 DTEND;TZID=Europe/Amsterdam:20251003T170000 DTSTAMP:20250731T045100Z URL:https://www.core-vision.nl/events/operating-systems-and-hypervisors-in -adaptive-socs-4/ SUMMARY:Operating Systems and Hypervisors in Adaptive SoCs DESCRIPTION:\nCourse Description\nThis course provides software developers options and techniques for selecting and implementing various types of ope rating systems and\nhypervisors on AMD Zynq™ UltraScale+™ and Versal ™ devices.\n\nThe emphasis is on:\n\n Exploring the capabilities of the application processing unit (APU) and real-time processing unit (RPU) rel ative to performance improvement and OS implementation\n Reviewing the ca talog of OS implementation options\, including Arm® TrustZone technology\ , hypervisors\, and various Linux implementations\n Applying various powe r management techniques for Zynq UltraScale+ and Versal devices\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/idirect-code-e1718949899167.webp CATEGORIES:AMD,Embedded,FPGA,KRIA,MPSoC,Versal,Vitis,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:744@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251103T090000 DTEND;TZID=Europe/Amsterdam:20251105T170000 DTSTAMP:20251013T061124Z URL:https://www.core-vision.nl/events/vhdl-for-designers-5/ SUMMARY:VHDL for Designers ✅ DESCRIPTION:✅ indicates CONFIRMED TO RUN courses\nCourse Description\nVHD L for Designers (Xilinx) prepares the engineer for practical project readi ness for FPGA designs. While the emphasis is on the practical VHDL-to-hard ware flow for FPGA devices\, this module also provides the essential found ation needed by ASIC and FPGA designers wishing to apply the more advanced features of VHDL covered in the next module.\n\nDelegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts\, example designs\, modules and constraint files to use\, adapt a nd extend on their own projects.\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/scripting.jpg CATEGORIES:Doulos,Hardware,VHDL LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:644@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251013T090000 DTEND;TZID=Europe/Amsterdam:20251015T170000 DTSTAMP:20250731T045917Z URL:https://www.core-vision.nl/events/accelerating-applications-with-the-v itis-unified-software-environment/ SUMMARY:Accelerating Applications with the Vitis Unified Software Environme nt DESCRIPTION:Course Description\nLearn how to develop\, debug\, and profile new or existing C/C++ and RTL applications in the Vitis™ unified softwar e environment targeting both data center and embedded applications.\n\nThe emphasis of this course is on:\n\n Using OpenCL™ APIs to run hardware kernels on Alveo™ accelerator cards\n Scheduling hardware kernels and c ontrolling data movement by using OpenCL APIs and the Xilinx Runtime libra ry for embedded platforms\n Demonstrating the Vitis environment GUI flow and makefile flow for both data center and embedded applications\n Descri bing the Vitis platform execution model and XRT\n Describing kernel devel opment using C/C++ and RTL\n Analyzing reports with the Vitis analyzer to ol\n Optimizing designs\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/11/Core-Vision-AI-article-2.webp CATEGORIES:AI,AMD,DSP,Embedded,FPGA,MPSoC,Versal,Vision,Vitis,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:645@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251016T090000 DTEND;TZID=Europe/Amsterdam:20251017T170000 DTSTAMP:20250731T052440Z URL:https://www.core-vision.nl/events/developing-ai-inference-solutions-wi th-the-vitis-ai-platform-2/ SUMMARY:Developing AI Inference Solutions with the Vitis AI Platform DESCRIPTION:Course Description\nImplement neural networks on cloud and edge platforms using the Vitis™ AI development platform.\n\nThe emphasis of this course is on:\n\n Illustrating the Vitis AI tool flow\, including op timization and compilation.\n Exploring the architectural features of the Deep Learning Processor Unit (DPU).\n Utilizing the Vitis AI Library to optimize pre-processing and post-processing functions.\n Creating a custo m platform and application.\n Deploying a design.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/11/Core-Vision-AI-article-2.webp CATEGORIES:AI,AMD,DSP,Embedded,FPGA,KRIA,MPSoC,Versal,Vitis,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:653@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251020T090000 DTEND;TZID=Europe/Amsterdam:20251021T170000 DTSTAMP:20250806T080910Z URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s oc-architecture-2/ SUMMARY:Designing with the Versal Adaptive SoC: Architecture DESCRIPTION:Course Description\nLearn about the AMD Versal™ adaptive SoC architecture building blocks\, such as the programmable logic\, high-speed I/O\, clocking\, processing system\, AI Engines\, and the programmable ne twork on chip (NoC). Also learn how to use leading-edge memory and interfa cing technologies to deliver powerful heterogeneous acceleration for any a pplication.\n\nThe emphasis of this course is on:\n\n Reviewing the archi tecture of the Versal adaptive SoC\n Describing the different compute res ources available in the Versal architecture\n Describing the architecture s of the network on chip (NoC) and AI Engine\n Outlining the memory solut ions and programming interfaces available in the Versal adaptive SoC\n Id entifying the PCI Express® and serial transceiver solutions available in the Versal adaptive SoC\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/08/versal-workshop-2024-take-2.jpg CATEGORIES:AI,AMD,Versal,Vitis LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:708@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251020T090000 DTEND;TZID=Europe/Amsterdam:20251021T170000 DTSTAMP:20250729T095307Z URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s oc-design-methodology-2/ SUMMARY:Designing with the Versal Adaptive SoC: Design Methodology DESCRIPTION:Course Description\nUse different AMD Versal™ adaptive SoC de sign methodologies and techniques for developing designs targeting Versal devices. Also learn how to apply application mapping and partitioning\, de sign closure\, power\, and thermal solutions to enhance the performance of a design.\nThe emphasis is on:\n\n Demonstrating the embedded software d evelopment flow for Versal devices\n Demonstrating the AI Engine developm ent flow\n Using the provided design tools and Versal adaptive SoC design methodologies to create complex systems\n Leveraging the Power Design Ma nager (PDM) tool for power estimation\n Identifying Versal adaptive SoC p ower and thermal solutions\n Enabling top-level RTL flows for Versal devi ces\n Applying common timing closure techniques\n Performing device conf iguration and debugging\n Improving Versal adaptive SoC system performanc e\n Performing system-level simulation\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpgavdes1-e1718949086246.png CATEGORIES:AMD,Embedded,FPGA,System,Timing Closure,Versal,Vitis,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:651@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251022T090000 DTEND;TZID=Europe/Amsterdam:20251022T170000 DTSTAMP:20250807T050237Z URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s oc-network-on-chip/ SUMMARY:Designing with the Versal Adaptive SoC: Network on Chip DESCRIPTION:Course Description\nThis course introduces the AMD Versal™ ne twork on chip (NoC) to users familiar with other SoC architectures. Beside s providing an overview of the major components in the Versal device\, the course illustrates how the NoC can be configured to access DDR memory con trollers and HBM memory controllers.\n\nThe emphasis of this course is on: \n\n Enumerating the major components comprising the NoC architecture in the Versal ACAP\n Implementing a basic Versal NoC design using the Vivado ™ IP integrator\n Accessing the Versal NoC using the modular NoC flow\n Configuring the DDR memory controller for accessing DDR memory\n Config uring and tunning the NoC for efficient data movement\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/08/versal-workshop-2024-take-2.jpg CATEGORIES:AI,AMD,Connectivity,System,Versal,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:771@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251023T093000 DTEND;TZID=Europe/Amsterdam:20251024T133000 DTSTAMP:20251014T042109Z URL:https://www.core-vision.nl/events/free-online-workshop-designing-with- the-versal-adaptive-soc-hardware-debug%e2%9c%85/ SUMMARY:Free Online Workshop: Designing with the Versal Adaptive SoC: Hardw are Debug✅ DESCRIPTION:\n\n✅ indicates CONFIRMED TO RUN\nWorkshop Description\nIn co llaboration with AMD\, Doulos\, Faster Technology and Core-Vision this fre e workshop Designing with the Versal Adaptive SoC: Hardware Debug and will be sponsored by AMD.\n\n\n\n\n\n\n\n\n\n\n\nThe Versal™ adaptive SoC fr om AMD is multi-featured\, offering unprecedented system level performance and integration.\n\n\n\n\n\n\n\n\n\n\n\n\nJoin us for a workshop which ex plores the tools and techniques available to debug AMD Versal™ devices. We'll investigate debugging the fabric and hard blocks\, as well as APIs w hich provide a Python interface for programming and debugging.\n\n\n\n\n\n \n\n\n\n\n\n\nThe workshop is designed to maximize individual engagement a nd learning.  Each attendee is encouraged to informally ask pertinent que stions throughout\, to actively participate in the learning process.\n\n\n \nWhat will I learn?\n\n\n\n\nThe workshop will provide you with an unders tanding of:\n\n The different tool flows for AMD Versal devices\n The de bug interfaces in the Versal devices\n The different debug IP cores\, suc h as the AXIS ILA and AXISVIO cores\n The different hard block debugging tools\n Versal device debugging techniques for JTAG lowspeed debug and hi gh-speed debug port (HSDP) debug\n ChipScoPy APIs for hardware debugging\ n\n\n\n\n\n\n\n\nRegister\n\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/versal-webinar.jpg CATEGORIES:AI,AMD,DSP,FPGA,IP,KRIA,ML,MPSoC,Versal,Vision,Vitis,Vivado,Wor kshop END:VEVENT BEGIN:VEVENT UID:652@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251024T090000 DTEND;TZID=Europe/Amsterdam:20251024T170000 DTSTAMP:20250806T081644Z URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s oc-quick-start-2/ SUMMARY:Designing with the Versal Adaptive SoC: Quick Start DESCRIPTION:Course Description\nExplore the AMD Versal™ adaptive SoC hete rogeneous architecture containing a programmable network on chip (NoC) and AI Engines and learn how to use different design tool flows targeting Ver sal devices. Gain knowledge of embedded software development and applicati on partitioning. Also learn how to perform system migration to the Versal architecture.\n\nThe emphasis of this course is on:\n\n Reviewing the arc hitecture of the Versal adaptive SoC\n Describing the different compute r esources available in the Versal architecture\n Demonstrating the embedde d software development flow for Versal devices\n Describing the architect ures of the network on chip (NoC) and AIEngine\n Explaining application p artitioning based on the models of computation\n Comparing various functi onal blocks of the Versal devices to previous-generation devices\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/08/versal-workshop-2024-take-2.jpg CATEGORIES:AI,AMD,Versal,Vitis LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:654@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251024T090000 DTEND;TZID=Europe/Amsterdam:20251024T170000 DTSTAMP:20250916T045027Z URL:https://www.core-vision.nl/events/designing-with-versal-ai-engine-dsp- applications-2/ SUMMARY:Designing with Versal AI Engine: DSP Applications DESCRIPTION:Course Description\nThis course covers the AMD Versal™ AI Eng ine architecture and using the AI Engine DSP Library\, system partitioning \, rapid prototyping\, and custom coding of AI Engine kernels. Developing AI Engine DSP designs using AMD Vitis™ Model Composer is also demonstrat ed.\n\nThe emphasis of this course is on:\n\n Providing an overview of th e AI Engine architecture\n Utilizing the Vitis DSP library for AI Engines \n Performing system partitioning and planning\n Adding custom kernel co de for designs\n Creating AI Engine DSP designs using Vitis Model Compose r\n Analyzing reports using the Analysis view of the Vitis Unified IDE\n\ n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/06/shutterstock_136710647-e1718948748220.jpg CATEGORIES:AI,AMD,DSP,FPGA,ML,Versal,Vision LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:660@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251024T090000 DTEND;TZID=Europe/Amsterdam:20251024T170000 DTSTAMP:20250807T071417Z URL:https://www.core-vision.nl/events/designing-with-versal-ai-engine-quic k-start/ SUMMARY:Designing with Versal AI Engine: Quick Start DESCRIPTION:Course Description\nThis course covers the AMD Versal™ AI Eng ine architecture and memory modules\, programming the AI Engine (kernels a nd graphs)\, using the DSP Library\, developing AI Engine designs using AM D Vitis™ Model Composer\, and debugging the AI Engines.\n\nThe emphasis of this course is on:\n\n Illustrating the AI Engine architecture and mem ory modules\n Describing the Vitis and AI Engine tool flow\n Programming the AI Engine with kernels and graphs\n Describing the AI Engine APIs\, including streaming data APIs\, and I/O buffers\n Utilizing the Vitis DSP library\n Creating AI Engine designs using Vitis Model Composer\n Descr ibing the debugging methodology for AI Engines\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/edge-ai-e1718949293991.png CATEGORIES:AI,AMD,DSP,FPGA,Versal,Vitis LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:648@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251027T090000 DTEND;TZID=Europe/Amsterdam:20251028T170000 DTSTAMP:20250807T052816Z URL:https://www.core-vision.nl/events/designing-with-versal-ai-engine-arch itecture-and-design-flow-1/ SUMMARY:Designing with Versal AI Engine: Architecture and Design Flow - 1 DESCRIPTION:Course Description\nThis course describes the AMD Versal™ AI Engine architecture\, the data communications within an AI Engine array an d between the PL and AI Engines\, how to program the AI Engines (single ke rnel programming and multiple kernel programming using data flow graphs)\, and how to analyze a kernel program by using various debugger features.\n \nThe emphasis of this course is on:\n\n Describing the AI Engine (AIE) a rchitecture\n Illustrating the Versal AI Engine tool flow\n Designing wi th single AI Engine kernels and analyzing the performance of scalar and ve ctorwized kernels using the Vitis™ unified software platform\n Designin g with multiple AI Engine kernels using data flow graphs with the Vitis Un ified IDE\n Reviewing the data movement between AI Engines\, between AI  Engines via memory and DMA\, and between AI Engines to programmable logic (PL)\n Analyzing and debugging kernel performance\n Describing the AIE- ML architecture\n Illustrating the programming model for the AIE-ML\n De scribing the AIE-ML v2 architecture for Versal AI Edge Series Gen 2 device s\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/edge-ai-e1718949293991.png CATEGORIES:AI,AMD,DSP,Versal,Vitis,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:650@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251029T090000 DTEND;TZID=Europe/Amsterdam:20251030T170000 DTSTAMP:20250909T120929Z URL:https://www.core-vision.nl/events/designing-with-versal-ai-engine-grap h-programming-with-ai-engine-kernels-2/ SUMMARY:Designing with Versal AI Engine: Graph Programming with AI Engine K ernels - 2 DESCRIPTION:Course Description\nThis course describes the system design flo w and interfaces that can be used for data movement in the AMD Versal™ A I Engine. It demonstrates how to utilize AI Engine APIs and the AI Engine DSP library for faster development. In addition\, advanced features in ada ptive data flow (ADF) graph implementation\, such as using streams\, casca de streams\, buffer location constraints\, runtime parameterization\, and APIs to update and read runtime parameters\, are covered. The course also highlights how to utilize the AMD Vitis™ Model Composer tool for AI Engi ne designs.\n\nThe emphasis of this course is on:\n\n Implementing a syst em-level design flow (PS + PL + AIE) and the supported simulation\n Using an interface for data movement between the PL and AI Engine\n Utilizing AI Engine APIs for arithmetic operations and advanced MAC intrinsics to im plement filters\n Utilizing the AI Engine DSP library for faster developm ent\n Applying advanced features for optimizing a system-level design\n Utilizing the Vitis Model Composer tool for AI Engine designs\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/edge-ai-e1718949293991.png CATEGORIES:AI,AMD,DSP,System,Versal,Vitis,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:677@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251031T090000 DTEND;TZID=Europe/Amsterdam:20251031T170000 DTSTAMP:20250909T121123Z URL:https://www.core-vision.nl/events/using-robotics-applications-with-the -kria-kr260-robotics-starter-kit-and-kria-robotics-stack-krs-3/ SUMMARY:Using Robotics Applications with the Kria KR260 Robotics Starter Ki t and Kria Robotics Stack (KRS) ✅ DESCRIPTION:✅ indicates CONFIRMED TO RUN courses\nCourse Description\nThi s course will help you learn about the Kria™ System-on-Module  (SOM) an d Kria KR260 Robotics Starter Kit\, enabling you to accelerate robotics-ba sed applications using the KR260 Starter Kit right out of the box without any installation or FPGA knowledge. The course also covers Robot Operating System 2 (ROS 2) and how to use the Kria Robotics Stack (KRS) and run pre -built accelerated robotics applications. Additionally\, design guidelines for developing your own carrier card are discussed.\n\nThe emphasis of th is course is on:\n\n Providing an overview of the Kria K26 SOM and its ad vantages\n Providing an overview of the Kria KR260 Robotics Starter Kit\, its interfaces\, and how to get started with the kit\n Describing the Ro bot Operating System (ROS) and Kria Robotics Stack (KRS) and how KRS enabl es roboticists to get up and running with ROS\n Running accelerated appli cations using an Ubuntu image:\n\n ROS 2 Multi-Node Communication via TSN accelerated application\n ROS 2 Perception Node accelerated application\ n 10 Gigabit Ethernet-based Machine Vision Camera accelerated application \n\n\n Reviewing design guidelines for developers to design their own car rier card\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/KR260_01.png CATEGORIES:AI,AMD,DSP,Embedded,FPGA,KRIA,MPSoC,Vision,Vitis,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:664@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251031T090000 DTEND;TZID=Europe/Amsterdam:20251031T170000 DTSTAMP:20251013T060921Z URL:https://www.core-vision.nl/events/migrating-from-ultrascale-devices-to -versal-adaptive-socs-2/ SUMMARY:Migrating from UltraScale+ Devices to Versal Adaptive SoCs DESCRIPTION:Course Description\nThis course illustrates the different appro aches for efficiently migrating existing designs to the AMD Versal™ adap tive SoC from AMD UltraScale+™ devices. The course also covers system de sign planning and partitioning methodologies as well as design migration c onsiderations for different system design types.\n\nThe emphasis of this c ourse is on:\n\n Identifying and comparing various functional blocks in t he Versal adaptive SoC to those in previous-generation UltraScale+ devices \n Reviewing the approaches for migrating existing designs to the Versal adaptive SoC\n Describing the development platforms for all developers\n Enabling top-level RTL flows for Versal devices\n Identifying design mig ration considerations for PL-only designs and Zynq™ UltraScale+ MPSoC de signs\n Specifying the recommended methodology for planning a system desi gn migration based on the system design type\n Discussing AI Engine syste m partitioning planning\n Migrating Zynq UltraScale+ MPSoC-based system-l evel designs to the Versal adaptive SoC\n Detailing Versal device hardwar e debug features\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/Versal_Product-Shot.jpg CATEGORIES:Board,Connectivity,DSP,FPGA,Hardware,System,Timing Closure,Versal,Vitis,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:770@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251103T090000 DTEND;TZID=Europe/Amsterdam:20251107T170000 DTSTAMP:20251021T102544Z URL:https://www.core-vision.nl/events/comprehensive-vhdl-5/ SUMMARY:Comprehensive VHDL ✅ DESCRIPTION:✅ indicates CONFIRMED TO RUN courses\nCourse Description\nCom prehensive VHDL is the industry standard 5-day training course teaching th e application of VHDL for FPGA and ASIC design. Fully updated and restruct ured to reflect current best practice\, engineers can attend either the in dividual modules\, or the full 5-day course.\n\n VHDL for Designers (days 1-3) prepares the engineer for practical project readiness for FPGA desig ns. While the emphasis is on the practical VHDL-to-hardware flow for FPGA devices\, this module also provides the essential foundation needed by ASI C and FPGA designers wishing to apply the more advanced features of VHDL c overed in the next module. Delegates targeting FPGAs will take away a flex ible project infra-structure which includes a set of scripts\, example des igns\, modules and constraint files to use\, adapt and extend on their own projects.\n Advanced VHDL (days 4-5) builds on the foundation of the pre vious module to prepare the engineer for complex FPGA or ASIC design. It f ocuses on the use of VHDL for large hierarchical designs\, design re-use\, and the creation of more powerful test benches.\n\nWorkshops comprise app roximately 50% of class time\, and are based around carefully designed exe rcises to reinforce and challenge the extent of learning.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/scripting.jpg CATEGORIES:Doulos,VHDL LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:662@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251103T090000 DTEND;TZID=Europe/Amsterdam:20251104T170000 DTSTAMP:20250703T104416Z URL:https://www.core-vision.nl/events/using-vision-based-applications-with -the-kria-kv260-vision-ai-starter-kit-system-on-module-2/ SUMMARY:Using Vision-based Applications with the Kria KV260 Vision AI Start er Kit & System-on-Module DESCRIPTION:Course Description\n This course will help you learn about the Xilinx Kria™ System-on-Module (SOM) and Kria KV260 Vision AI Starter Kit \, enabling you to accelerate vision-based applications using the KV260 St arter Kit right out of the box without any installation or FPGA knowledge. \n\n\nThe course also provides information on how you can build your own h ardware and software components\, customize an AI model\, and perform benc hmarking. In addition\, design guidelines for developing your own carrier card are covered.\n\n\nThe emphasis of this course is on:\n\n Providing a n overview of the Xilinx KriaK26 SOM and its advantages.\n Providing an o verview of the Xilinx KriaKV260 Vision AI Starter Kit and how to get start ed with the kit.\n Running accelerated applications\, such as the Smart C amera\, AI Box\, and Defect Detection applications\, using the kit.\n Run ning the NLP SmartVision demo application using the kit.\n Building the h ardware and software design components from scratch.\n Customizing the AI models used in the applications.\n Reviewing the design guidelines for d evelopers to design their own carrier card.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/KRIA-SOM-1.png CATEGORIES:AI,AMD,Board,Connectivity,DSP,Embedded,FPGA,Hardware,KRIA,ML,MP SoC,System,Vision,Vitis,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:732@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251105T090000 DTEND;TZID=Europe/Amsterdam:20251106T170000 DTSTAMP:20251013T050845Z URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s oc-memory-interfaces-2/ SUMMARY:Designing with the Versal Adaptive SoC: Memory Interfaces DESCRIPTION:Course Description\nThis course provides a system-level underst anding of AMD Versal™ adaptive SoC memory interfaces. Memory controller architecture\, IP generation\, simulation\, and implementation are covered . Additional information on PCB design issues is also covered\nThe emphasi s is on:\n\n Constructing a system using Versal adaptive SoC external mem ory interfaces by:\n\n Selecting the appropriate IP for an application\n Configuring the memory controller IPs\n Using the memory controllers in test benches and applications\n Simulating and implementing the memory co ntroller IPs\n\n\n Exploring traffic pattern generation\n Performance tu ning for the hardened DDRMC\n Accessing the appropriate reference materia l for board design issues involving signal integrity\, the power supply\, reference clocking\, and trace design\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/Versal_Product-Shot.jpg CATEGORIES:AMD,Board,Connectivity,Embedded,FPGA,Hardware,Versal,Vitis,Viva do LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:773@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251105T090000 DTEND;TZID=Europe/Amsterdam:20251106T170000 DTSTAMP:20251021T132826Z URL:https://www.core-vision.nl/events/designing-with-the-spartan-ultrascal e-fpga-architecture/ SUMMARY:Designing with the Spartan UltraScale+ FPGA: Architecture DESCRIPTION:Course Description\nLearn about the key features and architectu re of the AMD Spartan™ UltraScale+™ FPGA\, including its advanced I/O\ , high-speed transceivers\, substantial built-in and external memory\, PCI e® Gen4 connectivity\, and modern security. Recognize how these features provide a versatile\, cost-optimized\, and power-efficient platform for di verse applications.\nThe emphasis of this course is on:\n\n Describing th e key features and fundamental blocks of the Spartan UltraScale+ FPGA arch itecture\n Describing Spartan UltraScale+ clocking\, including buffer typ es\, clock management tiles\, and routing for enhanced timing\n Describin g the various on-chip memory resources available in the Spartan UltraScale + architecture\n Utilizing the advanced I/O capabilities for various conn ectivity needs\n Identifying the high-speed transceivers for use in appli cations such as PCIe Gen4\n Explaining the configuration process for Spar tan UltraScale+ devices\n Outlining the platform security framework and a dvanced security features\n Leveraging the Power Design Manager (PDM) too l for power estimation\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpga-vdes2-e1718949197527.png CATEGORIES:AMD,Digital Design,FPGA,Timing Closure,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:668@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251105T090000 DTEND;TZID=Europe/Amsterdam:20251106T170000 DTSTAMP:20251013T050643Z URL:https://www.core-vision.nl/events/designing-with-xilinx-serial-transce ivers-2/ SUMMARY:Designing with Xilinx Serial Transceivers DESCRIPTION:Course Description\nLearn how to employ serial transceivers in UltraScale™\, UltraScale+™ FPGA or Zynq® UltraScale+ MPSoC designs.\n The focus is on:\n\n Identifying and using the features of the serial tra nsceiver blocks\, such as 8B/10B and 64B/66B encoding\, channel bonding\, clock correction\, and comma detection.\n Utilizing the Transceivers Wiza rds to instantiate transceiver primitives.\n Synthesizing and implementin g transceiver designs.\n Taking into account board design as it relates t o the transceivers.\n Testing and debugging.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/high-speed-serial-banner-e1718949231123.png CATEGORIES:AMD,Connectivity,Embedded,FPGA,KRIA,MPSoC,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:746@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251106T090000 DTEND;TZID=Europe/Amsterdam:20251107T170000 DTSTAMP:20251013T050515Z URL:https://www.core-vision.nl/events/advanced-vhdl-4/ SUMMARY:Advanced VHDL ✅ DESCRIPTION:✅ indicates CONFIRMED TO RUN courses\nCourse Description\nAdv anced VHDL (2-days) builds on the foundation of the previous module (VHDL for Designers) to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs\, design re-use \, and the creation of more powerful test benches.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/scripting.jpg CATEGORIES:Doulos,Hardware,VHDL LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:734@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251107T090000 DTEND;TZID=Europe/Amsterdam:20251107T170000 DTSTAMP:20251013T050740Z URL:https://www.core-vision.nl/events/designing-with-the-versal-adaptive-s oc-serial-transceivers/ SUMMARY:Designing with the Versal Adaptive SoC: Serial Transceivers DESCRIPTION:Course Description\nThis course provides a system-level underst anding of AMD Versal™ adaptive SoC serial transceivers. Transceiver arch itecture\, IP generation\, simulation\, and implementation are covered. Ad ditional information on PCB design issues is also covered.\nThe focus is o n:\n\n Constructing a system using Versal device serial transceivers by:\ n▪ Selecting the appropriate IP for an application\n▪ Configuring Tran sceivers Wizard IPs\n▪ Using transceiver IP example designs\n▪ Simulat ing and implementing transceiver IPs\n Identifying the advanced capabilit ies of the serial transceivers\, including using IBERT and eye scan option s\n Accessing the appropriate reference material for board design issues involving signal integrity\, the power supply\, reference clocking\, and t race design\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/high-speed-serial-banner-e1718949231123.png CATEGORIES:Connectivity,FPGA,Versal,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:776@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251110T090000 DTEND;TZID=Europe/Amsterdam:20251111T170000 DTSTAMP:20251027T072845Z URL:https://www.core-vision.nl/events/designing-fpgas-using-the-vivado-des ign-suite-3/ SUMMARY:Designing FPGAs Using the Vivado Design Suite 3 DESCRIPTION:Course Description\nLearn how to effectively employ timing clos ure techniques.This course includes:\n\n Demonstrating timing closure tec hniques such as baselining\, pipelining\, and synchronization circuits.\n Showing optimum HDL coding techniques that help with design timing clo sure.\n Illustrating the advanced capabilities of the Vivado® logic ana lyzer to debug a design.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpga-vdes2-e1718949197527.png CATEGORIES:AMD,FPGA,IP,Timing Closure,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:775@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251110T090000 DTEND;TZID=Europe/Amsterdam:20251111T170000 DTSTAMP:20251027T072548Z URL:https://www.core-vision.nl/events/designing-fpgas-using-the-vivado-des ign-suite-1/ SUMMARY:Designing FPGAs Using the Vivado Design Suite 1 DESCRIPTION:Course Description\nThis course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flo w.\n\nThe course provides experience with:\n\n Creating a Vivado Design S uite project with source files.\n Simulating a design.\n Performing pin assignments.\n Applying basic timing constraints.\n Synthesizing and imp lementing.\n Debugging a design.\n Generating and downloading a bitstrea m onto a demo board.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpga-vdes2-e1718949197527.png CATEGORIES:AMD,Digital Design,FPGA,Timing Closure,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:779@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251112T090000 DTEND;TZID=Europe/Amsterdam:20251113T170000 DTSTAMP:20251103T120523Z URL:https://www.core-vision.nl/events/designing-fpgas-using-the-vivado-des ign-suite-2/ SUMMARY:Designing FPGAs Using the Vivado Design Suite 2 ✅ DESCRIPTION:✅ indicates CONFIRMED TO RUN courses\nCourse Description\nLea rn how to build a more effective FPGA design:\n\nThe focus is on:\n\n Usi ng synchronous design techniques.\n Utilizing the Vivado® IP integrator to create a sub-system.\n Performing power analysis and optimization to i mprove the power efficiency of a design.\n Reviewing and analyzing timing reports for a design.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpga-vdes2-e1718949197527.png CATEGORIES:AMD,Digital Design,FPGA,Timing Closure,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:767@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251112T090000 DTEND;TZID=Europe/Amsterdam:20251113T170000 DTSTAMP:20251027T073034Z URL:https://www.core-vision.nl/events/designing-fpgas-using-the-vivado-des ign-suite-4/ SUMMARY:Designing FPGAs Using the Vivado Design Suite 4 DESCRIPTION:Course Description\nLearn how to use the advanced aspects of th e Vivado® Design Suite and AMD Xilinx hardware.The focus is on:\n\n\n Applying timing constraints for source–synchronous and system–synchr onous interfaces.\n\n Utilizing floorplanning techniques.\n\n Employing advanced implementation options.\n\n Utilizing AMD Xilinx security fea tures.\n\n Identifying advanced FPGA configurations.\n\n Debugging a des ign at the device startup phase.\n Utilizing Tcl scripting when using the Vivado logic analyzer in a design.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpga-vdes2-e1718949197527.png CATEGORIES:AMD,Digital Design,FPGA,IP,Timing Closure,Vivado END:VEVENT BEGIN:VEVENT UID:777@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251117T090000 DTEND;TZID=Europe/Amsterdam:20251118T170000 DTSTAMP:20251027T073624Z URL:https://www.core-vision.nl/events/design-closure-techniques/ SUMMARY:Design Closure Techniques DESCRIPTION: indicates CONFIRMED TO RUN courses\nCourse Description\nLearn how to achieve design closure more efficiently and productively by using the three pillars of design closure (functional closure\, timing closure\, and power closure). Also learn how to solve functional behavior\, timing\ , and power simultaneously to achieve faster time-to-market results.\n\nTh e emphasis of this course is on:\n\n Defining what design closure is and describing the three pillars of design closure (functional closure\, timin g closure\, and power closure)\n Using recommended coding techniques ▪ Applying initial design checks and reviewing timing summary and methodolog y reports for a design\n Using baselining to verify that a design meets t iming goals and applying the guidelines described in the baselining proces s\n Performing quality of results (QoR) assessments at different stages t o improve the QoR score\n Implementing Intelligent Design Runs (IDR) to a utomate analysis and timing closure for complex designs\n Applying common timing closure techniques\n Optimizing SLR crossings in Versal SSIT devi ces\n Reviewing the importance of power closure and device selection\n E stimating power consumption by using the Vivado™ Design Suite Power Repo rt utility and performing power optimization on a design\n Identifying Ve rsal™ adaptive SoC power and thermal solutions\n Utilizing architecture features to improve a design's power consumption\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/06/shutterstock_1891148005-e1718949699580.jpg CATEGORIES:AMD,Digital Design,FPGA,Timing Closure,Versal LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:683@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251117T090000 DTEND;TZID=Europe/Amsterdam:20251118T170000 DTSTAMP:20251027T073402Z URL:https://www.core-vision.nl/events/designing-with-dynamic-function-exch ange-dfx-using-the-vivado-design-suite/ SUMMARY:Designing with Dynamic Function eXchange (DFX) Using the Vivado Des ign Suite DESCRIPTION:Course Description\nLearn how to construct\, implement\, and do wnload a Dynamic Function eXchange (DFX) FPGA design using the Vivado® De sign Suite. This course covers both the tool flow and mechanics of success fully creating a DFX design.\n\nThe emphasis of this course is on:\n\n Id entifying best design practices and understanding the subtleties of the DF X design flow \n Using DFX in AMD FPGAs and adaptive SoCs\n Implementing DFX designs using features such as block design containers (BDC)\, Abstra ct Shells\, and nested DFX\n Recognizing DFX design considerations for FP GAs and adaptive SoCs\n Using the DFX IPs in the DFX process\n Analyzing and floorplanning DFX designs\n Configuring devices using DFX\n Applyin g appropriate debugging techniques on DFX designs\n Implementing DFX in a n embedded system environment\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpga-dfx-e1718949533491.png CATEGORIES:AI,AMD,DSP,FPGA,IP,KRIA,System,Versal,Vivado LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:681@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251119T090000 DTEND;TZID=Europe/Amsterdam:20251120T170000 DTSTAMP:20251027T073422Z URL:https://www.core-vision.nl/events/ultrafast-design-methodology/ SUMMARY:UltraFast Design Methodology DESCRIPTION:Course Description\nLearn how to improve design speed and relia bility by using the UltraFast™ Design Methodology and the Vivado™ Desi gn Suite.\nThe focus is on:\n\n Optimizing system reset design and synchr onization circuits\n Employing best practice HDL coding techniques\n App lying appropriate timing closure techniques\n Reviewing an UltraFast Desi gn Methodology case study\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/fpgavdes1-e1718949086246.png CATEGORIES:AMD,DSP,FPGA,MPSoC,Versal,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:780@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251120T093000 DTEND;TZID=Europe/Amsterdam:20251121T133000 DTSTAMP:20251105T082208Z URL:https://www.core-vision.nl/events/free-online-workshop-designing-with- the-amd-versal-gen-2-architecture-%e2%9c%85/ SUMMARY:Free ONLINE Workshop: Designing with the AMD Versal Gen 2 Architect ure ✅ DESCRIPTION:\n\n✅ indicates CONFIRMED TO RUN\nWorkshop Description\n\n\n\ n\n\nIn this FREE WORKSHOP (delivered in 2 half day sessions) you will lea rn about the AMD Versal™ AI Edge Series Gen 2 and Prime Series Gen 2 ada ptive SoC architectures\, which combine programmable logic with a NEW high -performance processing system and next-generation AI Engines.Also learn h ow these devices facilitate end-to-end acceleration and maximize system pe rformance for embedded systems - all in a single device built on a foundat ion of enhanced safety and security.\n\n\n\n\n\n\n\n\n\n\n\nThe workshop i s designed to maximize individual engagement and learning.  Each attendee is encouraged to informally ask pertinent questions throughout\, to activ ely participate in the learning process.\n\n\n \;\n\n\n\nWhat will I l earn?\n\n\n\nThe emphasis of this workshop is on:\n\n\n Describing the di fferent compute resources available in the Versal adaptive SoC\n Explaini ng the new high-performance processing system (PS)\n Describing the next- generation AI Engine architecture\n Describing the network on chip (NoC) resources\n Outlining the available DDR5/LPDDR5X memory controller suppor t\n Reviewing the new image and video processing hard blocks\n Explainin g the functional safety and security enhancements\n Identifying the avail able PCI Express® Gen 5 and 32G high-speed serial transceiver solutions\n \n\n\n\n\n\n\n\n\nRegister\n\n\n\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/versal-webinar.jpg CATEGORIES:AI,AMD,DSP,FPGA,IP,KRIA,ML,MPSoC,Versal,Vision,Vitis,Vivado,Wor kshop END:VEVENT BEGIN:VEVENT UID:689@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251121T090000 DTEND;TZID=Europe/Amsterdam:20251121T170000 DTSTAMP:20251027T073504Z URL:https://www.core-vision.nl/events/migrating-to-the-vitis-embedded-soft ware-development-ide/ SUMMARY:Migrating to the Vitis Embedded Software Development IDE DESCRIPTION:Course Description\n\n\nThis course demonstrates the tools and techniques required for embedded software design and development using the AMD Vitis™ Unified IDE.The emphasis of this course is on:\n\n Reviewin g the basics of the embedded software development flow\n Exploring the te rminology and features of the Vitis Unified IDE\n Developing bare-metal a nd Linux® applications\n Debugging applications using the Vitis Unified IDE\n Using the Vitis Python™ command line interface\n Migrating from the classic Vitis IDE to the Vitis Unified IDE\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/idirect-code-e1718949899167.webp CATEGORIES:Embedded,FPGA,MicroBlaze,MPSoC,System,Versal,Vitis,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:685@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251124T090000 DTEND;TZID=Europe/Amsterdam:20251125T170000 DTSTAMP:20251027T073303Z URL:https://www.core-vision.nl/events/vitis-model-composer-a-matlab-and-si mulink-based-product/ SUMMARY:Vitis Model Composer: A MATLAB and Simulink-based Product DESCRIPTION:Course Description\nThis course provides experience with using the Vitis™ Model Composer tool for model-based designs.The course provid es experience with:\n\n Creating a model-based design using HDL\, HLS\, a nd AIE library blocks along with custom blocks in Vitis Model Composer\n Implementing DSP functions using Vitis Model Composer \n Utilizing design implementation tools\n Transforming algorithmic specifications to produc tion-quality IP implementations using automatic optimizations and leveragi ng the high-level synthesis technology of the Vitis HLS tool\n Creating V ersal™ AI Engine graphs and kernels using Vitis Model Composer\n Connec ting AI Engine blocks and non-AI Engine blocks\n Verifying and debugging AI Engine code using the Vitis analyzer\n Simulating and debugging a com plex system created using AI Engine library blocks\n Performing hardware validation using Vitis Model Composer\n Integrating an AI Engine design f rom Vitis Model Composer into the Vitis Unified IDE\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/06/shutterstock_136710647-e1718948748220.jpg CATEGORIES:AI,AMD,DSP,Hardware,IP,KRIA,MPSoC,System,Versal,Vitis,Vivado,Zy nq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:687@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251126T090000 DTEND;TZID=Europe/Amsterdam:20251127T170000 DTSTAMP:20250703T123819Z URL:https://www.core-vision.nl/events/high-level-synthesis-with-the-vitis- unified-ide/ SUMMARY:High-Level Synthesis with the Vitis Unified IDE DESCRIPTION:Course Description\nThis course provides a thorough introductio n to the Vitis™ High-Level Synthesis (HLS) tool. The focus is on:\n\n C onverting C/C++ designs into RTL implementations.\n Learning the Vitis HL S tool flow.\n Creating I/O interfaces for designs by using the Vitis HLS tool.\n Applying different optimization techniques.\n Improving through put\, area\, latency\, and logic by using different HLS pragmas/directives .\n Exporting IP that can be used with the Vivado® IP catalog.\n Migrat ing designs from the classic Vitis HLS tool to the Vitis Unified IDE.\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/vitis_hls-e1718948972516.png CATEGORIES:AI,AMD,DSP,FPGA,IP,KRIA,ML,MPSoC,Versal,Vitis,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:693@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251201T090000 DTEND;TZID=Europe/Amsterdam:20251202T170000 DTSTAMP:20250703T125913Z URL:https://www.core-vision.nl/events/embedded-systems-design/ SUMMARY:Embedded Systems Design DESCRIPTION:Course Description\nLearn general embedded concepts\, tools\, a nd techniques using the AMD Vivado™ Design Suite and AMD Vitis™ Unifie d IDE.The emphasis is on:\n\n Designing\, expanding\, and modifying embed ded systems utilizing the features and capabilities of the Zynq™ System on a Chip (SoC)\, Zynq UltraScale+™ MPSoC\, Versal™ adaptive SoC\, and MicroBlaze™ V soft processor\n Adding and simulating AXI-based periphe rals using bus functional model (BFM) simulation\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/embedded3-e1718948872404.webp CATEGORIES:AMD,Embedded,FPGA,KRIA,MicroBlaze,MPSoC,Versal,Vitis,Vivado,Zyn q LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:695@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251201T090000 DTEND;TZID=Europe/Amsterdam:20251202T170000 DTSTAMP:20251202T134735Z URL:https://www.core-vision.nl/events/embedded-heterogeneous-design/ SUMMARY:Embedded Heterogeneous Design DESCRIPTION:Course Description\nThis course covers the AMD Versal™ archit ecture and illustrates the tool flow for developing HLS and AI Engine comp onents as well as integrating an entire system project to design an embedd ed heterogeneous system using the v++ tools and AMD Vitis™ Unified IDE.T he emphasis of this course is on:\n\n\n Describing an embedded heterogene ous system design\n Illustrating the AMD Versal adaptive SoC architecture \, NoC\, and AI Engine\n Describing an AMD Versal design tool flow\n Dev eloping HLS and AIE components using the AMD Vitis tool\n Utilizing the v ++ command line tools for component compilation\, linking\, and packaging to run emulation\n Demonstrating the system design flow for a heterogeneo us embedded system using the AMD Vitis Unified IDE\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/08/versal-workshop-2024-take-2.jpg CATEGORIES:AMD,Embedded,FPGA,KRIA,MPSoC,Versal,Vitis,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:699@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251201T090000 DTEND;TZID=Europe/Amsterdam:20251202T170000 DTSTAMP:20250703T130515Z URL:https://www.core-vision.nl/events/zynq-ultrascale-mpsoc-for-the-hardwa re-designer/ SUMMARY:Zynq UltraScale+ MPSoC for the Hardware Designer DESCRIPTION:Course Description\nThis course provides hardware designers wit h an overview of the capabilities and support for the Zynq® UltraScale+ ™ MPSoC family from a hardware architectural perspective.The emphasis is on:\n\n Identifying the key elements of the application processing unit (APU) and real-time processing unit (RPU)\n Reviewing the various power d omains and their control structure\n Illustrating the processing system ( PS) and programmable logic (PL) connectivity\n Utilizing QEMU to emulate hardware behavior\n\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/08/MPSoC-e1725463185155.jpg CATEGORIES:AMD,Embedded,FPGA,MPSoC,Vivado,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:697@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251203T090000 DTEND;TZID=Europe/Amsterdam:20251205T170000 DTSTAMP:20250703T130255Z URL:https://www.core-vision.nl/events/embedded-systems-software-design/ SUMMARY:Embedded Systems Software Design DESCRIPTION:Course Description\nhis course introduces the concepts\, tools\ , and techniques required for software design and development for the AMD Zynq™ System on a Chip (SoC)\, Zynq UltraScale+™ MPSoC\, and Versal™ adaptive SoC architectures using the AMD Vitis™ Unified IDE.\nThe focus is on:\n\n Reviewing the basics of Vitis Unified IDE\n Customizing boar d support packages (BSPs) for resource access and management of the Xilinx Standalone library\n Utilizing device drivers effectively\n Developing software applications for the available processors\n Debugging and integr ating user applications\n Employing best practices to enable good design decisions\n\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/04/idirect-code-e1718949899167.webp CATEGORIES:AMD,Embedded,FPGA,KRIA,MPSoC,Versal,Vitis,Zynq LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:701@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251208T090000 DTEND;TZID=Europe/Amsterdam:20251209T170000 DTSTAMP:20251013T055438Z URL:https://www.core-vision.nl/events/expert-vhdl-design/ SUMMARY:Expert VHDL Design DESCRIPTION:Course Description\nExpert VHDL Design is a 2 days class part o f the intensive 5-day Expert VHDL class.\n\n Expert VHDL Design (2 days) is for design engineers wishing to deepen their knowledge of RTL synthesis using VHDL\, and to improve their VHDL coding style with design maintaina bility and re-use in mind. This section also includes the introduction to OVL/PSL.\n\nThe modules\, which may be attended together or independently\ , follow on from the industry standard class\, Comprehensive VHDL. Careful ly designed workshops comprise approximately 50% of teaching time\, and en able engineers to apply their new skills in the context of the latest VHDL design tools\, practices and methodologies.\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/scripting.jpg CATEGORIES:Doulos,VHDL LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VEVENT UID:702@core-vision.nl DTSTART;TZID=Europe/Amsterdam:20251208T090000 DTEND;TZID=Europe/Amsterdam:20251212T170000 DTSTAMP:20251210T150358Z URL:https://www.core-vision.nl/events/expert-vhdl/ SUMMARY:Expert VHDL DESCRIPTION:Course Description\nExpert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase productivity by en hancing their knowledge of the VHDL language itself and its application fo r design and verification. Presented in two distinct course modules\, Expe rt VHDL focuses on language and synthesis issues\, design maintainability and re-use\, structured verification environments and the latest technique s for verification - including an introduction to OVL/PSL and introduction s to OSVVM and UVVM.\n\n Expert VHDL Design (2 days) is for design engine ers wishing to deepen their knowledge of RTL synthesis using VHDL\, and to improve their VHDL coding style with design maintainability and re-use in mind. This section also includes the introduction to OVL/PSL.\n Expert V HDL Verification (3 days) is for design engineers and verification enginee rs involved in VHDL test bench development or behavioural modelling for th e purpose of functional verification. Advanced VHDL language constructs ar e presented using a practical testbench methodology as an example. The alt ernative OSVVM and UVVM methodologies are then introduced and all three me thodologies compared and contrasted.\n\nThe modules\, which may be attende d together or independently\, follow on from the industry standard class\, Comprehensive VHDL. Carefully designed workshops comprise approximately 5 0% of teaching time\,.and enable engineers to apply their new skills in th e context of the latest VHDL design tools\, practices and methodologies.\n ATTACH;FMTTYPE=image/jpeg:https://www.core-vision.nl/wp-content/uploads/20 24/03/scripting.jpg CATEGORIES:Doulos,VHDL LOCATION:Core-Vision\, Cereslaan 24\, Heesch\, Netherlands\, 5384 VT\, Nede rland X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=Cereslaan 24\, Heesch\, Net herlands\, 5384 VT\, Nederland;X-APPLE-RADIUS=100;X-TITLE=Core-Vision:geo: 0,0 END:VEVENT BEGIN:VTIMEZONE TZID:Europe/Amsterdam X-LIC-LOCATION:Europe/Amsterdam BEGIN:DAYLIGHT DTSTART:20250330T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20251026T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:DAYLIGHT DTSTART:20260329T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20261025T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:DAYLIGHT DTSTART:20270328T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20271031T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:DAYLIGHT DTSTART:20280326T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20281029T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:DAYLIGHT DTSTART:20290325T030000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT BEGIN:STANDARD DTSTART:20291028T020000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD END:VTIMEZONE END:VCALENDAR