Comprehensive Verilog

Standard Level – 4 days

 

Comprehensive Verilog is a 4-day training course teaching the application of the Verilog® Hardware Description Language for FPGA and ASIC design. The syllabus covers the Verilog language, coding for register transfer level (RTL) synthesis, developing test fixtures, and using Verilog tools in the FPGA or ASIC design flows. For those interested in FPGA design or prototyping, depending on your choice of FPGA vendor and course venue, we can teach you the complete design flow from writing Verilog source code down to programming a physical FPGA demo board.

The course includes a brief overview of SystemVerilog, but delegates wishing to learn SystemVerilog in depth should attend Comprehensive SystemVerilog or Modular SystemVerilog

Workshops comprise approximately 50% of class time, and are based around carefully designed exercises to reinforce and challenge the extent of learning.

Doulos is an independent company, enabling delegates to receive the benefit of objective tuition while learning in the context of their chosen tool and methodology. Leading tools supported by this course include:

Simulation Aldec Active HDL™ & Riviera-PRO™ Cadence Incisive® Mentor Graphics ModelSim® & Questa® Synopsys VCS®

Synthesis Synopsys Synplify Pro® Synopsys Design Compiler® Mentor Graphics Precision® RTL

The course includes specific lab support for tool sets from the leading FPGA vendors including the vendor’s native simulation and place-and-route tools.

The tool options available on a specific scheduled course may vary. Preferences can be selected in the booking process. Or please contact Doulos to discuss specific requirements.

Who should attend?

• Engineers about to embark on their first Verilog design project
• Engineers who have already acquired some practical experience in the use of Verilog, but wish to consolidate and extend their knowledge within a formal training environment using the tools of their choice.

 

What will you learn?

• How Verilog fits into the FPGA or ASIC design flow
• How to use the Verilog language for hardware design and logic synthesis
• How to write thorough Verilog text fixtures to verify your designs
• How to avoid common mistakes when coding Verilog for synthesis
• How to use the specific Verilog tool flow you will be using on your project for simulation, synthesis, and where appropriate, FPGA P&R.

 

Pre-requisites

Delegates should have a good working knowledge of digital hardware design, or have attended Essential Digital Design Techniques (or equivalent). No previous Verilog knowledge is required.

Course materials

Doulos Course materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:

• Fully indexed course notes creating a complete reference manual
• Workbook full of practical examples to help you apply your knowledge
• Doulos Golden Reference Guide for Verilog language, syntax, semantics and tips
• Tool tour guides (to support the tools and technologies used on the course).

 

Structure and Content

Introduction to Verilog

What is Verilog? • Scope of Verilog • Design flow for ASICs, CPLDs and FPGAs • Introduction to synthesis • Synchronous design • Timing constraints • Verilog books and internet resources

Modules

Modules & ports • Continuous assignments • Wire assignments • Comments • Names • Nets and strengths • Design hierarchy • Module instances • Primitive instances • Text fixtures • $monitor • Initial blocks • Variables

Nets and Values

Primitives • Wire assignments • Net types • Drive strengths • Logic values • Vectors • Numbers • Truncation • Signed numbers

Formatting, Timescale and Always

Output formatting • Timescales • Always blocks • $stop and $finish • Using wires and registers correctly

Always Blocks

RTL always blocks • Event control • Combinational logic sensitivity • If statements • Begin-end • Incomplete assignment and latches • FPGAs and latches • Unknown and don’t care • Conditional operator • Tristates

Procedural Statements

Case • casez • casex • full_case • parellel_case • For, repeat, while and forever loops • integers • Self-disabling blocks • Combinational logic synthesis

Clocks and Flipflops

Synthesising flip-flops & latches • Avoiding simulation race hazards • Nonblocking assignments • Asynchronous & synchronous resets • Clock enables • Synthesizable always templates • RTL synthesis technology • Inferring flip-flops • Making best use of RTL synthesis

Operators and Parameters

Bitwise, reduction, logical and equality operators • Part selects • Concatenation & replication • Shift registers • Conditional compilation • include • Parameters • localparam • Hierarchical names

FSM Synthesis

State transition diagrams • State machine architectures • FSM timing • Coding FSMs in Verilog • State encoding • One-hot state machines • Unreachable states & safe design practices

Arithmetic and Synthesis

Arithmetic operators and their synthesis • Vector arithmetic • Bit-length of expressions • Signed and unsigned values • Adder architectures • WYSIWYG arithmetic synthesis • Arithmetic optimization • Resource sharing

Tasks, Functions and Memories

Tasks • Task argument passing • Static vs automatic storage • Synthesis of tasks • Functions • Verilog memories • RAM modelling and synthesis • Inference vs instantiation • $readmemb and $readmemh • generate for/if/case •

File I/O

Writing to files • $display • $strobe • $write • $monitor • Opening a closing files • File descriptors • Reading from files • $fscanf • Raw file I/O • $fgets • $fgetc • $fseek • $ftell

Functional Simulation

Design flow through to P&R • Gate-level simulation • Back annotation using SDF.• PLD and ASIC design flow • Verilog libraries • Command-line options • Test benches • Comparing actual vs expected outputs • Behavioural modelling

Behavioural Verilog

Algorithmic coding • real • event control • wait • Named events • Fork & join • External disable • Intra-assignment timing controls • Overcoming clock skew • Continuous procedural assignment • defparam • Hierarchical names

Specialised Topics

Structural Verilog • Using built-in primitives • Gate, net & path delays • Specify blocks • State-dependent delays • Pulse rejection • Cell library modelling • library • liblist • config • The Verilog PLI • PLI applications • PLI routines • The PLI in practice • The VPI

SystemVerilog

Overview of SystemVerilog • Status of SystemVerilog • RTL enhancements • Interfaces • Assertions • Testbenches • C interface