Clock Domain Crossing

indicates CONFIRMED TO RUN

 

  • Date: Friday February 24, 2023
  • Duration: 1 hour (with live Q&A)
  • Time: 11am – 12pm (CET)
  • Presenter: Charles Gardiner
  • Cost: Free!

Overview:

The primary goal in safely implementing any IC or FPGA project is to achieve a synchronous design. This implies that the relationship of all clocks and asynchronous resets to each other is defined in the synthesis constraints. Incorrect handling of clock-domain crossing (CDC) is probably the primary cause of sporadic errors, which are impossible to catch in a digital simulation and can cause a system to inexplicably fail in the field.

This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.

Topics include:

  • What causes metastability
  • How to correctly implement CDC logic for simple signals, complex data and counters
  • How to use Synopsys Design Constraints (SDC) to ensure that static timing analysis (STA) produces reliable results in the context of multi-clock designs

The webinar will also feature a working example from Microchip® using PolarFire® FPGAs and SoCs and the Libero® SoC Design Suite.

Charles Gardiner – Doulos Certified Training Instructor – will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.

Doulos


Datum
24 februari 2023

Locatie
Webinar
Online

Webinar

Prijs
€ 0,00

Informatie
Training brochure

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