Clock Domain Crossing
✅ indicates CONFIRMED TO RUN
- Date: Friday February 24, 2023
- Duration: 1 hour (with live Q&A)
- Time: 11am – 12pm (CET)
- Presenter: Charles Gardiner
- Cost: Free!
The primary goal in safely implementing any IC or FPGA project is to achieve a synchronous design. This implies that the relationship of all clocks and asynchronous resets to each other is defined in the synthesis constraints. Incorrect handling of clock-domain crossing (CDC) is probably the primary cause of sporadic errors, which are impossible to catch in a digital simulation and can cause a system to inexplicably fail in the field.
This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.
- What causes metastability
- How to correctly implement CDC logic for simple signals, complex data and counters
- How to use Synopsys Design Constraints (SDC) to ensure that static timing analysis (STA) produces reliable results in the context of multi-clock designs
Charles Gardiner – Doulos Certified Training Instructor – will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.