XIlinx ACAP devices
Aankomende Evenementen
- Designing with the Versal ACAP: Network on Chip - 03/02/2023 - 09:00 - 17:00
- Design Closure Techniques ✅ - 16/02/2023 - 17/02/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Architecture and Design Flow (1) - 07/03/2023 - 08/03/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) - 09/03/2023 - 10/03/2023 - 09:00 - 17:00
- Design Closure Techniques - 20/03/2023 - 21/03/2023 - 09:00 - 17:00
- Accelerating Applications with the Vitis Unified Software Environment - 27/03/2023 - 29/03/2023 - 09:00 - 17:00
- Designing with the IP Integrator Tool - 28/04/2023 - 09:00 - 17:00
- Designing with the Versal ACAP: Architecture and Methodology - 12/06/2023 - 14/06/2023 - 09:00 - 17:00
- Designing with the Versal ACAP: Network on Chip - 15/06/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Architecture and Design Flow (1) - 15/06/2023 - 16/06/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) - 19/06/2023 - 20/06/2023 - 09:00 - 17:00
- Accelerating Applications with the Vitis Unified Software Environment - 21/06/2023 - 23/06/2023 - 09:00 - 17:00
- Designing with Versal AI Engine 1: Architecture and Design Flow - 12/01/2050 - 09:00 - 17:00
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels - 12/01/2050 - 10:00 - 18:00
- Designing with the Versal ACAP: Architecture and Methodology - 12/01/2050 - 12:00 - 20:00
- Designing with the Versal ACAP: Network on Chip - 12/01/2050 - 13:00 - 21:00