XIlinx ACAP devices
Aankomende Evenementen
- Designing with the Versal ACAP: Architecture and Methodology - 19/06/2023 - 21/06/2023 - 09:00 - 17:00
- Designing with the Versal ACAP: Network on Chip - 22/06/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Architecture and Design Flow (1) - 22/06/2023 - 23/06/2023 - 09:00 - 17:00
- Accelerating Applications with the Vitis Unified Software Environment - 26/06/2023 - 28/06/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) - 29/06/2023 - 30/06/2023 - 09:00 - 17:00
- Designing with the IP Integrator Tool - 18/08/2023 - 09:00 - 17:00
- Design Closure Techniques - 21/08/2023 - 22/08/2023 - 09:00 - 17:00
- Adaptive SoCs for System Architects - 28/08/2023 - 29/08/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Architecture and Design Flow (1) - 11/09/2023 - 12/09/2023 - 09:00 - 17:00
- Zynq UltraScale+ MPSoC: Boot and Platform Management - 11/09/2023 - 12/09/2023 - 09:00 - 17:00
- Designing with Versal AI Engine: Graph Programming with AI Engine Kernels (2) - 13/09/2023 - 14/09/2023 - 09:00 - 17:00
- Accelerating Applications with the Vitis Unified Software Environment - 18/09/2023 - 20/09/2023 - 09:00 - 17:00
- Designing with the Versal ACAP: Network on Chip - 04/10/2023 - 09:00 - 17:00
- Designing with Versal AI Engine 1: Architecture and Design Flow - 12/01/2050 - 09:00 - 17:00
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels - 12/01/2050 - 10:00 - 18:00
- Designing with the Versal ACAP: Architecture and Methodology - 12/01/2050 - 12:00 - 20:00
- Designing with the Versal ACAP: Network on Chip - 12/01/2050 - 13:00 - 21:00