AMD Vivado FPGA and Archicture courses offered by Core|Vision
Aankomende Evenementen
- High-Level Synthesis with the Vitis Unified IDE - 06/05/2024 - 07/05/2024 - 09:00 - 17:00
- Developing AI Inference Solutions with the Vitis AI Platform - 21/05/2024 - 22/05/2024 - 09:00 - 17:00
- Using Vision-based Applications with the Kria KV260 Vision AI Starter Kit & System-on-Module - 21/05/2024 - 22/05/2024 - 09:00 - 17:00
- Design Closure Techniques - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Designing with the IP Integrator Tool - 12/06/2024 - 13/06/2024 - 09:00 - 17:00
- Xilinx Partial Reconfiguration Tools & Techniques - 01/01/2050 - 09:00 - 17:00
- Designing with the UltraScale and UltraScale+ Architectures - 01/01/2050 - 10:00 - 18:00
- UltraFast Design Methodology - 01/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 1 - 02/01/2050 - 09:00 - 17:00
- Designing FPGAs Using the Vivado Design Suite 2 - 02/01/2050 - 10:00 - 18:00
- Designing FPGAs Using the Vivado Design Suite 3 - 02/01/2050 - 11:00 - 19:00
- Designing FPGAs Using the Vivado Design Suite 4 - 02/01/2050 - 12:00 - 20:00
- Designing with the 7 Series Families - 05/01/2050 - 09:00 - 17:00
- Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite - 05/01/2050 - 10:00 - 18:00
- Accelerating Applications with the Vitis Unified Software Environment - 11/01/2050 - 12:00 - 20:00
- Designing with Versal AI Engine 1: Architecture and Design Flow - 12/01/2050 - 09:00 - 17:00
- Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels - 12/01/2050 - 10:00 - 18:00
- Designing with the Versal ACAP: Architecture and Methodology - 12/01/2050 - 12:00 - 20:00
- Designing with the Versal ACAP: Network on Chip - 12/01/2050 - 13:00 - 21:00
- Developing AI Inference Solutions with the Vitis AI Platform - 13/01/2050 - 09:00 - 17:00