Bug discovery by static analysis in VERILOG
- Date: Thursday June 17, 2021
- Duration: 25 min (with live Q&A)
- Time: 11:00 – 11:25 (CET)
- Presenter: Dr Reuven Dobkin
- Attendance: FREE!
During this short webinar, we will exemplify a few buggy RTL patterns that can be discovered by an automatic static analysis, leading to prompt bug-fix instead of a much longer verification by simulation / formal analyses.
Patterns to be discussed:
- Signal contention
- FSM issues: unreachable, trap states
- Tri-state buffers issues
If you have any queries, please contact email@example.com
17 juni 2021
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