Asynchronous reset synchronization – basics

✅ indicates CONFIRMED TO RUN

• Date: Wednesday June 21, 2023
• Duration: 30 min (with live Q&A)
• Time: 11:00 – 11:30 (CET)
  
• Presenter: Dr Reuven Dobkin
  
• Attendance: FREE!

Webinar Overview

Asynchronous resets are traditionally employed in VLSI designs for bringing synchronous circuitry to a known state after power up. Asynchronous reset release operation must be coordinated with the synchronous logic clock signal to eliminate synchronization failures due to possible contention between the reset and the clock. A lack of such coordination leads to intermittent failures on power up. During the webinar we will review basic implementation approaches for asynchronous reset synchronization.

If you have any queries, please contact info@vsyncc.com