Asynchronous reset synchronization – basics
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- Date: Wednesday June 21, 2023
- Duration: 30 min (with live Q&A)
- Time: 11:00 – 11:30 (CET)
- Presenter: Dr Reuven Dobkin
- Attendance: FREE!
Asynchronous resets are traditionally employed in VLSI designs for bringing synchronous circuitry to a known state after power up. Asynchronous reset release operation must be coordinated with the synchronous logic clock signal to eliminate synchronization failures due to possible contention between the reset and the clock. A lack of such coordination leads to intermittent failures on power up. During the webinar we will review basic implementation approaches for asynchronous reset synchronization.
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21 June 2023