Asynchronous reset synchronization – advanced

 

indicates CONFIRMED TO RUN

  • Date: Wednesday December 6, 2023
  • Duration: 30 min (with live Q&A)
  • Time: 11:00 – 11:30 (CET)
  • Presenter: Dr Reuven Dobkin
  • Attendance: FREE!

Webinar Overview

Asynchronous resets must be correctly synchronized to eliminate timing violations. The asynchronous reset synchronization becomes non-trivial, when considering large designs with fast clocking. During the webinar we will review advanced methods for asynchronous reset synchronization, dealing with high fanout and high-speed FPGA and ASIC designs.

If you have any queries, please contact info@vsyncc.com

vSync Circuits


Datum
06 december 2023

Locatie
Webinar
Online

Webinar

Prijs
€ 0,00

Informatie
Training brochure

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