Advanced Features and Techniques of Embedded Systems Design

Course Description

Advanced Features and Techniques of Embedded Systems Design provides embedded systems developers the necessary skills to develop complex embedded systems and enables them to improve their designs by using the tools available in the Vivado® IP Integrator. This course also helps developers understand and utilize advanced components of embedded systems design for architecting a complex system in the Zynq® All Programmable System on a Chip (SoC) or MicroBlaze™ soft processor.

This course builds on the skills gained in the Embedded Systems Design course. Labs provide hands-on experience with developing, debugging, and simulating an embedded system. Utilizing memory resources and implementing high-performance DMA are also covered. Labs use demo boards in which designs are downloaded and verified.

advedkLevel

Embedded Hardware 4

Training Duration

2 days

Audience

Hardware, firmware, and system design engineers who are interested in Xilinx embedded systems development flow

Prerequisites

  • Embedded Systems Design course or experience with embedded systems design and the Vivado Design Suite
  • Basic C programming
  • Working knowledge of the Zynq All Programmable SoC or MicroBlaze processor

Software Tools

  • Vivado Design or System Edition 2017.3

Hardware

  • Architecture: Zynq-7000 All Programmable SoC and 7 series FPGAs*
  • Demo board: Zynq-7000 All Programmable SoC ZC702 or ZedBoard or Kintex®-7 FPGA KC705 board*

* This course focuses on the Zynq-7000 All Programmable SoC and 7 series FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Skills Gained

After completing this comprehensive training, you will know how to:

  • Assemble an advanced embedded system
  • Take advantage of the various features of Zynq All Programmable SoC and Kintex™ FPGAs, Cortex™-A9 and MicroBlaze processors, including the AXI interconnect and various memory controllers
  • Apply advanced debugging techniques, including the use of the Vivado analyzer tool for debugging an embedded processor system and HDL system simulation for processor-based designs
  • Identify the steps involved in integrating a memory controller into an embedded system using the Cortex-A9 and MicroBlaze processors
  • Integrate an interrupt controller and interrupt handler into an embedded design
  • Design a flash memory-based system and boot load from off-chip flash memory

Course Outline

Day 1

  • Overview of Embedded Hardware Development {Demo}
  • Hardware-Software Flow {Lab}
  • Software Overview
  • Zynq-7000 All Programmable SoC Architecture Overview {Lab, Demo}
  • MicroBlaze Processor Architecture Overview {Lab}
  • Zynq UltraScale+ MPSoC Overview {Lab, Demo}
  • Debugging
    • Hardware Introduction {Demo}
    • Hardware – Marking Nets {Lab}
    • Hardware – Software Co-Debugging (Cross-Triggering) {Lab}
  • Memory Types
    • Memory Overview
    • Block RAM Controllers
    • Static Memory Controllers
    • DDRx Memory Operation
    • Dynamic Memory Controller (Zynq-7000 Device)
  • Interrupt Concepts
    • Introduction to Interrupts
    • Interrupts and the Zynq-7000 Device
    • General Interrupt Controller
    • Interrupts and the MicroBlaze Processor
    • AXI Interrupt Controller for the MicroBlaze Processor

Day 2

  • AXI Concepts
    • ○AXI Streaming: Introduction
    • ○MicroBlaze Processor Streaming Ports
    • ○AXI Streaming FIFO
    • ○Connecting AXI IP {Demo}
    • ○DMA
  • Zynq-7000 Device PS-PL Interface {Demo}
  • PS Peripherals
    • ○High-Speed: USB
    • ○High-Speed: Gigabit Ethernet {Lab}
    • ○Low-Speed: Overview {Lab}
    • ○Low-Speed: CAN {Demo}
    • ○Low-Speed: I2C
    • ○Low-Speed: SD/SDIO
    • ○Low-Speed: SPI
    • ○Low-Speed: UART {Demo}
  • Utility Logic
  • Sharing PS Resources (Hardware Perspective) {Lab}
  • Multi-Processor Hardware Architecture
  • Caching
  • Processor Caching and SCLR
  • Accelerator Coherency Port
  • Booting
    • ○Flow
    • ○PL {Lab}
    • ○Flash Image Generation
  • QEMU: Introduction {Demo}

Topic Descriptions

  • Lab 1: Building a Complete System (Zynq AP SoC and MicroBlaze Processor) – Develop hardware that incorporates the Zynq All Programmable SoC PS or MicroBlaze processor IP cores to interface to AXI GPIO peripherals and serial communication. Use the SDK development tools to create an embedded software application project for the hardware built.
  • Lab 2: Debugging on the Zynq All Programmable SoC – Evaluate debugging the hardware and software components of a Zynq All Programmable SoC design.
  • Lab 3: Extending Memory Space with Block RAM (Zynq AP Soc) – Use the Vivado IP integrator to extend the memory resources for the Cortex-A9 processor.
  • Lab 4: Extending Memory Space with a DDR3 controller (MicroBlaze Processor) – Use the Vivado IP integrator to extend the memory resources for the MicroBlaze processor.
  • Lab 5: Configuring DMA on the Zynq All Programmable SoC – Program the DMA controller on the Zynq All Programmable SoC PS and explore the various Standalone library services that support the Zynq All Programmable SoC PS DMA controller.
  • Lab 6: Boot Loading from Flash Memory (Zynq AP Soc) – Develop an application that is stored in flash memory, load it through a boot loader program, and execute a software application from external memory for the Cortex-A9 Processor.
  • Lab 7: Simulating an Embedded Processor System (MicroBlaze Processor) – Develop the process of simulating a complete design including an embedded system component using the Vivado simulator. Use SDK to create a new workspace/software application project and build a simple software application that will be included in the simulation.
  • Lab 8: Sharing PS Resources with a MicroBlaze Processor – Add peripherals to a Zynq All Programmable SoC design and connect the PS to a PL processor (i.e., a MicroBlaze processor to share PS resources). Generate the netlists and bitstream of the complete design.

Embedded


Datum
06 maart 2019 - 07 maart 2019

Locatie
Core|Vision
Cereslaan 10b
5384 VT
Heesch

Prijs
€ 1.500,00
of
18 Xilinx Training Credits

Informatie
Training brochure

Registratieformulier

EMBD ADV HW

€ 1.500,00