Training

Sharing is the new multiplying. Therefore, we regularly share our information and knowledge, even with our colleagues and competitors. As AMD Authorized Training Provider and Doulos Certified Training Partner, we offer a variety of FPGA training courses to broaden or deepen your knowledge. Furthermore, we are always ready to assist in solving complex issues.

Below you can find our training schedule. If the desired training is not listed or the date does not fit into your schedule, please contact us.

December 2025

Expert VHDL

Expert VHDL

08 December 2025 - 12 December 2025
09:00 - 17:00
Course Description Expert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase productivity by enhancing their knowledge of the VHDL [...]
Expert VHDL

Expert VHDL

08 December 2025 - 12 December 2025
09:00 - 17:00
Course Description Expert VHDL is an intensive 5-day advanced application class. It teaches engineers how to increase productivity by enhancing their knowledge of the VHDL [...]
Expert VHDL Design

Expert VHDL Design

08 December 2025 - 09 December 2025
09:00 - 17:00
Course Description Expert VHDL Design is a 2 days class part of the intensive 5-day Expert VHDL class. Expert VHDL Design (2 days) is for [...]
Expert VHDL Design

Expert VHDL Design

08 December 2025 - 09 December 2025
09:00 - 17:00
Course Description Expert VHDL Design is a 2 days class part of the intensive 5-day Expert VHDL class. Expert VHDL Design (2 days) is for [...]
Expert VHDL Verification

Expert VHDL Verification

10 December 2025 - 12 December 2025
09:00 - 17:00
Course Description Expert VHDL Verification is a 3 days course as part of the intensive 5-day Expert VHDL class. Expert VHDL Verification (3 days) is [...]
Expert VHDL Verification

Expert VHDL Verification

10 December 2025 - 12 December 2025
09:00 - 17:00
Course Description Expert VHDL Verification is a 3 days course as part of the intensive 5-day Expert VHDL class. Expert VHDL Verification (3 days) is [...]
Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2: Architecture

Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2: Architecture

15 December 2025 - 16 December 2025
09:00 - 17:00
€2.000,00
 / 20 Training Credits
Course Description Learn about the AMD Versal™ AI Edge Series Gen 2 and Prime Series Gen 2 adaptive SoC architectures, which combine programmable logic with [...]
Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2: Architecture

Designing with the Versal AI Edge Series Gen 2 and Prime Series Gen 2: Architecture

15 December 2025 - 16 December 2025
09:00 - 17:00
€2.000,00
 / 20 Training Credits
Course Description Learn about the AMD Versal™ AI Edge Series Gen 2 and Prime Series Gen 2 adaptive SoC architectures, which combine programmable logic with [...]

April 2026

Essential Digital Design Techniques

Essential Digital Design Techniques

09 April 2026 - 10 April 2026
09:00 - 17:00
€2.225,00
 / 34 Training Credits
Course Description Essential Digital Design Techniques is a fast-track,.application orientated course designed to bridge the gap between text book theory and real world digital design [...]

June 2026

Designing FPGAs Using the Vivado Design Suite 2

Designing FPGAs Using the Vivado Design Suite 2

03 June 2026 - 04 June 2026
09:00 - 17:00
€2.000,00
 / 20 Training Credits
Course Description Learn how to build a more effective FPGA design: The focus is on: Using synchronous design techniques. Utilizing the Vivado® IP integrator to [...]
Designing FPGAs Using the Vivado Design Suite 2

Designing FPGAs Using the Vivado Design Suite 2

03 June 2026 - 04 June 2026
09:00 - 17:00
€2.000,00
 / 20 Training Credits
Course Description Learn how to build a more effective FPGA design: The focus is on: Using synchronous design techniques. Utilizing the Vivado® IP integrator to [...]

September 2026

Designing FPGAs Using the Vivado Design Suite 1

Designing FPGAs Using the Vivado Design Suite 1

29 September 2026 - 30 September 2026
09:00 - 17:00
€2.000,00
 / 20 Training Credits
Course Description This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow. The course provides experience [...]

January 2030

Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite

Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite. This course covers both [...]
Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite

Designing with Dynamic Function eXchange (DFX) Using the Vivado Design Suite

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to construct, implement, and download a Dynamic Function eXchange (DFX) FPGA design using the Vivado® Design Suite. This course covers both [...]
Designing with the UltraScale and UltraScale+ Architectures

Designing with the UltraScale and UltraScale+ Architectures

On request
€2.000,00
 / 20 Training Credits
Course Description This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers. The emphasis is on: Introducing CLB resources, clock management [...]
Designing with the UltraScale and UltraScale+ Architectures

Designing with the UltraScale and UltraScale+ Architectures

On request
€2.000,00
 / 20 Training Credits
Course Description This course introduces the UltraScale™ and UltraScale+™ architectures to both new and experienced designers. The emphasis is on: Introducing CLB resources, clock management [...]
UltraFast Design Methodology

UltraFast Design Methodology

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to improve design speed and reliability by using the UltraFast™ Design Methodology and the Vivado™ Design Suite. The focus is on: [...]
UltraFast Design Methodology

UltraFast Design Methodology

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to improve design speed and reliability by using the UltraFast™ Design Methodology and the Vivado™ Design Suite. The focus is on: [...]
Designing FPGAs Using the Vivado Design Suite 1

Designing FPGAs Using the Vivado Design Suite 1

On request
€2.000,00
 / 20 Training Credits
Course Description This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow. The course provides experience [...]
Designing FPGAs Using the Vivado Design Suite 1

Designing FPGAs Using the Vivado Design Suite 1

On request
€2.000,00
 / 20 Training Credits
Course Description This course offers introductory training on the Vivado® Design Suite and helps you to understand the FPGA design flow. The course provides experience [...]
Designing FPGAs Using the Vivado Design Suite 2

Designing FPGAs Using the Vivado Design Suite 2

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to build a more effective FPGA design: The focus is on: Using synchronous design techniques. Utilizing the Vivado® IP integrator to [...]
Designing FPGAs Using the Vivado Design Suite 2

Designing FPGAs Using the Vivado Design Suite 2

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to build a more effective FPGA design: The focus is on: Using synchronous design techniques. Utilizing the Vivado® IP integrator to [...]
Designing FPGAs Using the Vivado Design Suite 3

Designing FPGAs Using the Vivado Design Suite 3

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to effectively employ timing closure techniques.This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits. Showing optimum HDL [...]
Designing FPGAs Using the Vivado Design Suite 3

Designing FPGAs Using the Vivado Design Suite 3

On request
€2.000,00
 / 20 Training Credits
Course Description Learn how to effectively employ timing closure techniques.This course includes: Demonstrating timing closure techniques such as baselining, pipelining, and synchronization circuits. Showing optimum HDL [...]
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