Online Webinar: RTL development under Verilog coding style requirements

Free Online Webinar: RTL development under Verilog coding style requirements

• Date: Wednesday December 11, 2024
  
• Duration: 30min (with live Q&A)
• Time: 11:00 – 11:30 (CET)
  
• Presenter: Dr Reuven Dobkin
  
• Attendance: FREE!

Webinar Overview

An appropriate Verilog coding style can minimize integration issues between design modules, optimize synthesis results, and improve code readability. We present an automated approach to handle coding style for multiple key features, enabling swift code analysis and management.

If you have any queries, please contact info@vsyncc.com