Migrating from UltraScale+ Devices to Versal Adaptive SoCs

Level

ACAP 2

What's New for 2024.2

• Added Versal RF series details in the Architecture Overview for Existing Users module
• Introduced the Advanced Flow for Versal implementation and the modular NoC flow in the Design Tool Flow module
• Added new modules:
• NoC Introduction and Concepts
• Enabling Top-level RTL Flows
• Added new labs:
• NoC Introduction and Concepts
• Using the Modular NoC Flow in an RTL Design
• Using the GT Wizard Subsystem
• Added Advanced Flow information in the Programmable Logic Design Migration Considerations module
• Introduced early-access segmented configuration feature in the Processing System Comparison module
• All labs have been updated to the latest software versions

Course Duration

1 day

Audience

Software and hardware developers, system architects, and anyone who needs to migrate their designs to Versal devices

Prerequisites

• Familiarity with designing UltraScale+ FPGAs and adaptive SoCs
• Familiarity with the AMD Vivado™ and Vitis™ tools

Software Tools

• Vitis Unified IDE 2024.2
• Vivado™ Design Suite 2024.2

Hardware

• Architecture:  Versal adaptive SoC

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

• Identify the different functional blocks in the AMD Versal adaptive SoC
• Utilize high-level system migration steps for efficient migration to the Versal adaptive SoC
• Describe the different tool flows for the Versal adaptive SoC
• Implement a basic Versal NoC design
• Utilize top-level RTL flows such as the modular NoC flow and GT subsystem flow for Versal devices
• Apply design migration guidelines for PL-only and PS+PL designs
• Follow the system design planning methodology
• Describe the AI Engine architecture and programming model as well as follow the AIE system partitioning methodology
• Migrate AMD Zynq UltraScale+ MPSoC system-level designs to the Versal adaptive SoC
• Describe the different debugging options available for the Versal adaptive SoC

Course Outline

Day 1

• Architecture Overview for Existing Users - Introduces to students who already have familiarity with AMD SoC architectures the new and updated features found in the Versal devices. Also provides an overview of the Versal portfolio. {Lecture}
• System Design Migration Approach - Describes important system design migration considerations and the high-level system steps for efficient migration to the Versal adaptive SoC. Also compares various functional blocks in the Versal adaptive SoC to those in previous-generation devices. {Lecture}
• Design Tool Flow - Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture}
• NoC Introduction and Concepts - Covers the reasons to use the network on chip, its basic elements, design entry flows, and common terminology. {Lecture, Lab}
• Enabling Top-level RTL Flows - Discusses two RTL-centric flows: One for accessing the NoC from RTL, known as the modular NoC flow, and another for the gigabit transceivers with the GT Wizard Subsystem flow. {Lecture, Labs}
• Programmable Logic Design Migration Considerations - Describes Versal adaptive SoC architectural enhancements as well as key programmable logic design migration considerations and best practices. Also covers the advantages of the Advanced Flow for Versal devices. {Lecture, Labs}
• Processing System Comparison - Describes Versal adaptive SoC processing system architectural differences. It covers the differences in the boot sequence between Versal and Zynq UltraScale+ devices. Also introduces the segmented configuration feature for Versal devices. {Lecture}
• System Design Planning Methodology - Describes system design planning, power, and thermal guidelines. Also reviews system debug, verification, and validation planning. {Lecture}
• AI Engine Architecture Overview and Programming - Discusses the Versal AI Engine architecture and explains the programming model for AI Engines with kernels and graph. {Lecture}
• AI Engine System Partitioning - Describes the AI Engine system partitioning and planning methodology and mapping system requirements. {Lecture, Lab}
• System-level Design Migration - Demonstrates how to migrate a Zynq UltraScale+ MPSoC system-level design to the Versal adaptive SoC. Also shows how to implement the same system design on the Versal AI Engine. {Lab}
• Debug Overview - Describes the tools and techniques available to debug PL and hard blocks in Versal devices. Also covers ChipScoPy APIs, which provide a Python™ interface to program and debug Versal devices. {Lecture}