This course provides a thorough introduction to the Vitis™ High-Level Synthesis (HLS) tool. The focus is on:
Converting C/C++ designs into RTL implementations.
Learning the Vitis HLS tool flow.
Creating I/O interfaces for designs by using the Vitis HLS tool.
Applying different optimization techniques.
Improving throughput, area, latency, and logic by using differentHLS pragmas/directives.
Exporting IP that can be used with the Vivado® IP catalog.
Migrating designs from the classic Vitis HLS tool to the Vitis Unified IDE.
What's New for 2024.1
Added a module and lab dedicated to the Vitis HLS Code Analyzer
All labs have been updated to the latest software versions
Level
DSP 3
Course Duration
2 days.
Audience
Software and hardware engineers looking to utilize high-level synthesis.
Prerequisites
C, C++, or System C knowledge.
High-level synthesis for software engineers OR high-level synthesis for hardware engineers.
Software Tools
Vitis HLS tool 2024.1
Vivado Design Suite 2024.1
Vitis Unified IDE 2024.1
Hardware
Architecture: Zynq® UltraScale+™ MPSoC and Versal® AI Core series series*
Demo board: Zynq UltraScale+ MPSoC ZCU104 board*
* This course focuses on the Zynq UltraScale+ MPSoC architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
Skills Gained
After completing this comprehensive training, you will know how to:
Enhance productivity by using the Vivado HLS tool.
Describe the high-level synthesis flow.
Use the Vitis Unified IDE to create an HLS component.
Identify the importance of the testbench.
Use directives to improve performance and area and select RTL interfaces.
Perform system-level integration of IP generated by the Vitis Unified IDE.
Migrate designs from the classic Vitis HLS tool to the Vitis Unified IDE.
Course Outline
Day 1
Introduction to High-Level Synthesis – Provides an overview of high-level synthesis (HLS), the Vitis Unified IDE for HLS flow, and the verification advantage. {Lecture}
HLS Component Development Flow – Explores the HLS component development flow in the Vitis Unified IDE. {Lecture, Lab}
Abstract Parallel Programming Model for HLS - Describes the structuring of a design atahigh level using anabstract parallel programming model. {Lecture}
Design Exploration with Directives – Explore different optimization techniques that can improve the design performance. {Lecture}
HLS Component Development Using the Command Line - Describes the unified command line interface and the the v++ and vitis-run commands. {Lecture, Lab}
Introduction to Vitis HLS Design Methodology – Introduces the methodology guidelines covered in this course and the HLS Design Methodology steps. {Lecture}
Introduction to I/O Interfaces – Explains interfaces such as block-level and port-level protocols abstracted by the Vitis HLS tool from the C design. {Lecture}
Block-Level Protocols – Explains the different types of block-level protocols abstracted by the Vitis HLS tool. {Lecture, Lab}
Port-Level I/O Protocols – Describes the port-level interface protocols abstracted by the Vitis HLS tool from the C design. {Lecture, Demo, Lab}
AXI4 Adapter Interface Protocols – Explains the different AXI interfaces (such as AXI4-Master, AXI4-Lite (Slave), and AXI4-Stream) supported by the Vitis HLS tool. {Lecture, Demo}
Vitis HLS Code Analyzer - Provides an overview of the Vitis Code Analyzer, its features, and how to view generated reports. {Lecture, Lab}
Day 2
Optimizing for Performance: PIPELINE – Describes the PIPELINE directive for improving the throughput of a design. {Lecture, Lab}
Optimizing for Performance: DATAFLOW – Describes the DATAFLOW directive for improving the throughput of a design by pipelining the functions to execute as soon as possible. {Lecture, Lab}
Optimizing for Throughput – Identify theperformance limitations caused by arrays in yourdesign. You will also explore optimization techniques to handlearrays for improving performance. {Lecture, Demo, Lab}
Optimizing for Latency: Default Behavior – Describes the default behavior of the Vitis HLS tool on latency and throughput. {Lecture}
Optimizing for Latency: Reducing Latency – Describes how to optimize the C design to improve latency. {Lecture}
Optimizing for Area and Logic - Describes different methods for improving resource utilization and explains how some of the directives have impact on the area utilization. {Lecture, Lab}
Optimizing AXI System Performance - Describes AXI burst transfers and their types. Also outlines the optimization steps to improve system performance. {Lecture}
Vitis HLS Libraries - Describes the library support offered by Vitis HLS. {Lecture}
Vitis HLS Libraries: Arbitrary Precision Data Types - Describes Vitis HLS support for the C/C++ languages as well as arbitrary precision data types. {Lecture, Lab}
Using Pointers in Vitis HLS - Explains the use of pointers in a design and workarounds for some of the limitations. {Lecture}
HLS Component Design Flow - System Integration - Illustrates the process of developing and exporting an HLS component as Vivado IP. {Lab}
Migrating to the Vitis Unified IDE - HLS Component - Describes the need for the Vitis Unified IDE and identifies different approaches for migrating projects from the classic Vitis HLS tool to the Vitis Unified IDE. {Lecture, Lab}
Request
Reservations can no longer be made for this event.