This course introduces the AMD Versal™ network on chip (NoC) to users familiar with other SoC architectures. Besides providing an overview of the major components in the Versal device, the course illustrates how the NoC can be configured to access DDR memory controllers and HBM memory controllers.
The emphasis of this course is on:
Enumerating the major components comprising the NoC architecture in the Versal ACAP
Implementing a basic Versal NoC design using the Vivado™ IP integrator
Accessing the Versal NoC using the modular NoC flow
Configuring the DDR memory controller for accessing DDR memory
Configuring and tunning the NoC for efficient data movement
What's New for 2025.1
Architecture Overview for Existing Users module: Added Versal AI Edge Series Gen 2 and Prime Series Gen 2 details
NoC DDR Memory Controller module: Added NoC DDR5 memory controller support and configuration details
Added a new lab on Introduction to the AXI NoC2 and DDRMC5
NoC Performance Tuning module: Added information on configuring multi-phase NoC modesAdded Versal RF series details in the Architecture Overview for Existing Users module
All labs have been updated to the latest software versions
Level
VER 2
Course Duration
1 day
Audience
Hardware developers and system architects whether migrating from existing AMD SoC devices or starting out with the Versal devices
Prerequisites
Any SoC or Versal adaptive SoC architecture course
Familiarity with the Vivado™ Design Suite
Familiarity with the Vitis™ Unified IDE
Software Tools
Vivado Design Suite 2025.1
Vitis unified IDE 2025.1
Hardware
Architecture: Versal adaptive SoCs
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Identify the major network on chip components in the AMD Versal architecture
Include the necessary components to access the NoC from the PL
Access the Versal NoC resources using the IP integrator and/or modular NoC flow
Design with the NoC and integrated DDR memory controller
Configure connection QoS for efficient data movement
Course Outline
Architecture Overview for Existing Xilinx Users – Introduces to students that already have familiarity with Xilinx architectures to the new and updated features found in the Versal ACAP devices. {Lecture
NoC Introduction and Concepts – Reviews the basic vocabulary and high–level operations of the NoC. {Lecture, Lab}
NoC Architecture – Provides the first deep dive into the sub–blocks of the NoC and how they are used. Describes how the NoC is accessed from the programmable logic. {Lecture}
Design Tool Flow – Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly. {Lecture}
Modular NoC Flow - Introduces the modular NoC flow for accessing Versal NoC resources. Also discusses modular NoC flow-supported use cases. {Lecture, lab}
NoC DDR Memory Controller –The integration between the NoC pathways and the DDR memory controllers must be understood to have efficient data movement on and off chip. This discussion of the NoC’s DDR memory controller blocks provides the background for properly selecting and configuring DDR memory and the memory controller for effective use. {Lecture}
NoC HBM Controller - Describes the high-bandwidth memory (HBM) controller architecture and identifies the steps for HBM controller configuration. {Lecture}
NoC Performance Tuning – Synthesizes everything about the NoC and its DDRMCs, illustrating how to fine tune the NoC for the best performance. {Lecture, Lab}
