* This course focuses on the UltraScale architectures.Check with your local Authorized Training Provider for specifics orother customizations.
Skills Gained
After completing this comprehensive training, you will have the necessary skills to:
Analyze a timing report to identify how to center the clock in the data eye
Apply appropriate techniques to reduce logic and net delay and to improve clock skew and clock uncertainty
Implement Intelligent Design Runs (IDR) to automate analysis and timing closure for complex designs
Utilize floorplanning techniques to improve design performance
Employ advanced implementation options, such as incremental compile flow, physical optimization techniques, and re-entrant mode as last mile strategies
Utilize security features, bitstream encryption, and authentication using AES for design and IP security
Identify advanced FPGA configurations, such as daisy chain and gangs, for configuring multiple FPGAs in a design
Debug a design at the device startup phase to debug issues related to startup events, .such as MMCM lock and design coming out of reset
Utilize Tcl scripting when using the Vivado logic analyzer in a designs
Course Outline
Day 1
UltraFast Design Methodology: Timing Closure – Introduces the UltraFast methodology guidelines on designclosure. {Lecture}
Hierarchical DesignOverview of the hierarchical design flows inthe Vivado DesignSuite. {Lecture}
Incremental Compile FlowUtilize the incremental compile flow when making last–minute RTLchanges. {Lecture, Lab}
Vivado Design Suite ECO FlowUse the ECO flow to make changes to a previously implementeddesign and applychanges to the original design. {Lecture, Lab}
Managing IP in Remote LocationsStore IP and related files remote to the current working projectdirectory. {Lecture, L
Timing Closure Using Physical Optimization TechniquesUse physical optimization techniques for timing closure. {Lecture,Lab}
Reducing Logic DelayDescribes how to optimize regular fabric paths and paths withdedicated blocks and macro primitives. {Lecture}
Reducing Net DelayReviews different techniques to reduce congestion and net delay.{Lecture}
Improving Clock SkewDescribes how to apply various techniques to improve clockskew. {Lecture}
Improving Clock UncertaintyReviews various flows for improving clock uncertainty, includingusing parallel BUFGCE_DIV clock buffers, changing MMCM orPLL settings, and limiting synchronous clock domaincrossing(CDC) paths. {Lecture, Lab}
Intelligent Design Runs (IDR) – Introduces Intelligent Design Runs (IDR), which are special types of implementation runs that use a complex flow to attempt to close timing. {Lecture, Lab}
Power Management Techniques – Describes the techniques used for low power design. {Lecture}
Day 2
Introduction to FloorplanningIntroduction to floorplanning and how to use Pblocks whilefloorplanning. {Lecture}
Design Analysis and FloorplanningExplore the pre–and post–implementation design analysisfeatures of the Vivado IDE. {Lecture, Lab}
CongestionIdentifies congestion and addresses congestion issues. {Lecture}
Daisy Chains and Gangs in ConfigurationIntroduces advanced configuration schemes for multiple FPGAs.{Lecture}
Bitstream SecurityUnderstand theAMD Xilinxbitstream security features such asreadback disable, bitstream encryption, and authentication.{Lecture, Demo}
Vivado Design Suite Debug MethodologyUnderstand and follow the debug core recommendations. Employthe debug methodology for debugging a design using the Vivadologic analyzer. {Lecture}
Trigger and Debug at Device StartupDebug the events around the device startup. {Lecture, Demo}
Trigger Using the Trigger State Machine in the Vivado LogicAnalyzerUse trigger state machine code to trigger the ILA and capturedata in the Vivado logic analyzer. {Lecture, Lab}
Introduction to the Vivado StoreIntroduces the Xilinx Vivado Store. {Lecture, Demo}
Scripting in Vivado Design Suite Non–Project ModeWrite Tcl commands in the non–project batch flow for a design.{Lecture, Lab}
Debugging the Design Using Tcl CommandsUse Tcl scripting for VLA designs for adding probes and makingconnections to probes. {Lecture, Lab}
Using Procedures in Tcl ScriptingEmploy procedures in Tcl scripting. {Lecture}
Using Lists in Tcl ScriptingEmploy lists in Tcl scripting. {Lecture}
Debugging and Error Handling in Tcl ScriptsUnderstand how to debug errors in a Tcl script. {Lecture}