Advanced VHDL (2-days) builds on the foundation of the previous module (VHDL for Designers) to prepare the engineer for complex FPGA or ASIC design. It focuses on the use of VHDL for large hierarchical designs, design re-use, and the creation of more powerful test benches.
Audience
Engineers who wish to become skilled in the practical use of VHDL for FPGA or ASIC design
Engineers who are about to embark on the first VHDL design project
Engineers who have already acquired some practical experience in the use of VHDL, but wish to consolidate and extend their knowledge within a training environment
What will you learn?
Advanced VHDL
The VHDL language concepts constructs essential for complex FPGA and ASIC design
The VHDL language constructs and coding styles that enable sophisticated test benches
How to code hierarchical designs using multiple VHDL design libraries
How to write re-usable, parameterisable VHDL code by exploiting generics and data types
How to run gate-level simulations
Request
Reservations can no longer be made for this event.