On October 8, 2019, the 21st edition of the Design Automation & Embedded Systems Event took place at the Van der Valk Hotel in Eindhoven. During the annual D&E Event, Frank de Bont gave a lecture about Static Timing Analysis in a nutshell.

With the complexity and size of FPGAs, development times also increase considerably. Much of the development time of the FPGA is spent on verification. The entire verification process consists of various steps. Components that are included in the verification process range include timing analysis, internal and external simulation and in-system testing.

Static timing analysis (STA) is a method for calculating the expected timing of a digital circuit without requiring simulations of the entire circuit. Every step in a design must be analyzed with regard to time specifications. Time related errors can be detected faster and easier by STA.

The presentation explains how STA works. Attention is also paid to clock domain crossing and an explanation is given when a generated and / or virtual clock should be used. A very useful presentation for not just starting developers.

This presentation can now be downloaded: “Static Timing Analysis in a nutshell”

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